 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ? 2006 microchip technology inc. ds41159e pic18fxx8 data sheet 28/40-pin high-performance, enhanced flash microcontrollers with can module
ds41159e-page ii ? 2006 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, linear active thermistor, mindi, miwi, mpasm, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powe rtool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2006, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona, gresham, oregon and mountain view, california. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ? 2006 microchip technology inc. ds41159e-page 1 pic18fxx8 high-performance risc cpu: ? linear program memory addressing up to 2mbytes ? linear data memory addressing to 4 kbytes ? up to 10 mips operation ? dc ? 40 mhz clock input ? 4 mhz-10 mhz oscillator/clock input with pll active ? 16-bit wide instructions, 8-bit wide data path ? priority levels for interrupts ? 8 x 8 single-cycle hardware multiplier peripheral features: ? high current sink/source 25 ma/25 ma ? three external interrupt pins ?timer0 module: 8-bit/16-bit timer/counter with 8-bit programmable prescaler ?timer1 module: 16-bit timer/counter ?timer2 module: 8-bit timer/counter with 8-bit period register (time base for pwm) ?timer3 module: 16-bit timer/counter ? secondary oscillator clock option ? timer1/timer3 ? capture/compare/pwm (ccp) modules; ccp pins can be configured as: - capture input: 16-bit, max resolution 6.25 ns - compare: 16-bit, max resolution 100 ns (t cy ) - pwm output: pwm resolution is 1 to 10-bit max. pwm freq. @:8-bit resolution = 156 khz 10-bit resolution = 39 khz ? enhanced ccp module which has all the features of the standard ccp module, but also has the following features for advanced motor control: - 1, 2 or 4 pwm outputs - selectable pwm polarity - programmable pwm dead time ? master synchronous serial port (mssp) with two modes of operation: - 3-wire spi? (supports all 4 spi modes) -i 2 c? master and slave mode ? addressable usart module: - supports interrupt-on-address bit advanced analog features: ? 10-bit, up to 8-channel analog-to-digital converter module (a/d) with: - conversion available during sleep - up to 8 channels available ? analog comparator module: - programmable input and output multiplexing ? comparator voltage reference module ? programmable low-voltage detection (lvd) module: - supports interrupt-on-low-voltage detection ? programmable brown-out reset (bor) can bus module features: ? complies with iso can conformance test ? message bit rates up to 1 mbps ? conforms to can 2.0b active spec with: - 29-bit identifier fields - 8-byte message length - 3 transmit message buffers with prioritization - 2 receive message buffers - 6 full, 29-bit acceptance filters - prioritization of acceptance filters - multiple receive buffers for high priority messages to prevent loss due to overflow - advanced error management features special microcontroller features: ? power-on reset (por), power-up timer (pwrt) and oscillator start-up timer (ost) ? watchdog timer (wdt) with its own on-chip rc oscillator ? programmable code protection ? power-saving sleep mode ? selectable oscillator options, including: - 4x phase lock loop (pll) of primary oscillator - secondary oscillator (32 khz) clock input ? in-circuit serial programming tm (icsp tm ) via two pins flash technology: ? low-power, high-speed enhanced flash technology ? fully static design ? wide operating voltage range (2.0v to 5.5v) ? industrial and extended temperature ranges 28/40-pin high-performanc e, enhanced flash microcontrollers with can pic18fxx8 ds41159e-page 2 ? 2006 microchip technology inc. pin diagrams device program memory data memory i/o 10-bit a/d (ch) comparators ccp/ eccp (pwm) mssp usart timers 8/16-bit flash (bytes) # single-word instructions sram (bytes) eeprom (bytes) spi? master i 2 c? pic18f248 16k 8192 768 256 22 5 ? 1/0 y y y 1/3 pic18f258 32k 16384 1536 256 22 5 ? 1/0 y y y 1/3 pic18f448 16k 8192 768 256 33 8 2 1/1 y y y 1/3 pic18f458 32k 16384 1536 256 33 8 2 1/1 y y y 1/3 rb7/pgd rb6/pgc rb5/pgm rb4 rb3/canrx rb2/cantx/int2 rb1/int1 rb0/int0 v dd v ss rd7/psp7/p1d rd6/psp6/p1c rd5/psp5/p1b rd4/psp4/eccp1/p1a rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3/c2in- rd2/psp2/c2in+ mclr /v pp ra0/an0/c vref ra1/an1 ra2/an2/v ref - ra3/an3/v ref + ra4/t0cki ra5/an4/ss /lvdin re0/an5/rd re1/an6/wr /c1out re2/an7/cs /c2out v dd v ss osc1/clki osc2/clko/ra6 rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl rd0/psp0/c1in+ rd1/psp1/c1in- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic18f458 pdip rb3/canrx nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3/c2in- rd2/psp2/c2in+ rd1/psp1/c1in- rd0/psp0/c1in+ rc3/sck/scl rc2/ccp1 1 pic18f458 plcc rc1/t1osi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 rb2/cantx/int2 rb1/int1 rb0/int0 v dd rd7/psp7/p1d v ss rd6/psp6/p1c rd5/psp5/p1b rd4/psp4/eccp1/p1a rc7/rx/dt ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0/cv ref mclr /v pp nc rb7/pgd rb6/pgc rb5/pgm rb4 nc ra4/t0cki ra5/an4/ss /lvdin re0/an5/rd re1/an6/wr /c1out re2/an7/cs /c2out v dd v ss osc1/clki osc2/clko/ra6 nc rc0/t1oso/t1ck1 pic18f448 pic18f448 ? 2006 microchip technology inc. ds41159e-page 3 pic18fxx8 pin diagrams (continued) pic18f458 tqfp rb7/pgd spdip, soic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 rb6/pgc rb5/pgm rb4 rb3/canrx rb2/cantx/int2 rb1/int1 rb0/int0 v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda mclr /v pp ra0/an0/cv ref ra1/an1 ra2/an2/v ref - ra3/an3/v ref + ra4/t0cki ra5/an4/ss /lvdin v ss osc1/clki osc2/clko/ra6 rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl pic18f248 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 12 rc7/rx/dt rd4/psp4/eccp1/p1a rd5/psp5/p1b rd6/psp6/p1c rd7/psp7/p1d v ss v dd rb0/int0 rb1/int1 rb2/cantx/int2 rb3/canrx nc nc rb4 rb5/pgm rb6/pgc rb7/pgd mclr /v pp ra0/an0/cv ref ra1/an1 ra2/an2/v ref - ra3/an3/v ref + nc rc0/t1oso/t1cki osc1/clki v ss v dd re2/an7/cs /c2out re1/an6/wr /c1out osc2/clko/ra6 re0//an5/rd ra5/an4/ss /lvdin ra4/t0cki rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3/c2in- rd2/psp2/c2in+ rd1/psp1/c1in- rd0/psp0/c1in+ rc3/sck/scl rc2/ccp1 rc1/t1osi nc pic18f448 pic18f258 pic18fxx8 ds41159e-page 4 ? 2006 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................. 7 2.0 oscillator configurations ................................................................................................... ......................................................... 17 3.0 reset ....................................................................................................................... ................................................................... 25 4.0 memory organization ......................................................................................................... ........................................................ 37 5.0 data eeprom memory ......................................................................................................... ................................................... 59 6.0 flash program memory........................................................................................................ ...................................................... 65 7.0 8 x 8 hardware multiplier................................................................................................... ......................................................... 75 8.0 interrupts .................................................................................................................. .................................................................. 77 9.0 i/o ports ................................................................................................................... .................................................................. 93 10.0 parallel slave port ........................................................................................................ ............................................................ 107 11.0 timer0 module .............................................................................................................. ........................................................... 109 12.0 timer1 module .............................................................................................................. ........................................................... 113 13.0 timer2 module .............................................................................................................. ........................................................... 117 14.0 timer3 module .............................................................................................................. ........................................................... 119 15.0 capture/compare/pwm (ccp) modules .......................................................................................... ....................................... 123 16.0 enhanced capture/compare/pwm (eccp) module................................................................................. ............................... 131 17.0 master synchronous serial port (mssp) module ............................................................................... ..................................... 143 18.0 addressable universal synchronous asynchr onous receiver transmitter (usart)................................................ .............. 183 19.0 can module ................................................................................................................. ............................................................ 199 20.0 compatible 10-bit analog-to-digital converter (a/d) module ................................................................. ................................. 241 21.0 comparator module.......................................................................................................... ........................................................ 249 22.0 comparator voltage reference module ........................................................................................ ........................................... 255 23.0 low-voltage detect ......................................................................................................... ......................................................... 259 24.0 special features of the cpu ................................................................................................ .................................................... 265 25.0 instruction set summary .................................................................................................... ...................................................... 281 26.0 development support........................................................................................................ ....................................................... 323 27.0 electrical characteristics ................................................................................................. ......................................................... 329 28.0 dc and ac characteristics graphs and tables ................................................................................ ....................................... 361 29.0 packaging information...................................................................................................... ........................................................ 377 appendix a: data sheet revision history........................................................................................ .................................................. 385 appendix b: device differences................................................................................................. ........................................................ 385 appendix c: device migrations .................................................................................................. ........................................................ 386 appendix d: migrating from other picmicro ? devices ..................................................................................................................... 38 6 index .......................................................................................................................... ........................................................................ 387 on-line support................................................................................................................ ................................................................. 397 systems information and upgrade hot line ....................................................................................... ............................................... 397 reader response ................................................................................................................ .............................................................. 398 pic18fxx8 product identification system........................................................................................ ................................................. 399 ? 2006 microchip technology inc. ds41159e-page 5 pic18fxx8 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/doc umentation issues become known to us, we will publis h an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. pic18fxx8 ds41159e-page 6 ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. ds41159e-page 7 pic18fxx8 1.0 device overview this document contains device specific information for the following devices: ? pic18f248 ? pic18f258 ?pic18f448 ?pic18f458 these devices are available in 28-pin, 40-pin and 44-pin packages. they are differentiated from each other in four ways: 1. pic18fx58 devices have twice the flash program memory and data ram of pic18fx48 devices (32 kbytes and 1536 bytes vs. 16 kbytes and 768 bytes, respectively). 2. pic18f2x8 devices implement 5 a/d channels, as opposed to 8 for pic18f4x8 devices. 3. pic18f2x8 devices implement 3 i/o ports, while pic18f4x8 devices implement 5. 4. only pic18f4x8 devices implement the enhanced ccp module, analog comparators and the parallel slave port. all other features for devices in the pic18fxx8 family, including the serial communications modules, are identical. these are summarized in table 1-1. block diagrams of the pic18f2x8 and pic18f4x8 devices are provided in figure 1-1 and figure 1-2, respectively. the pinouts for these device families are listed in table 1-2. table 1-1: pic18fxx8 device features features pic18f248 pic18f258 pic18f448 pic18f458 operating frequency dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz internal program memory bytes 16k 32k 16k 32k # of single-word instructions 8192 16384 8192 16384 data memory (bytes) 768 1536 768 1536 data eeprom memory (bytes) 256 256 256 256 interrupt sources 17 17 21 21 i/o ports ports a, b, c ports a, b, c ports a, b, c, d, e ports a, b, c, d, e timers 4 4 4 4 capture/compare/pwm modules 1 1 1 1 enhanced capture/compare/ pwm modules ?? 1 1 serial communications mssp, can, addressable usart mssp, can, addressable usart mssp, can, addressable usart mssp, can, addressable usart parallel communications (psp) no no yes yes 10-bit analog-to-digital converter 5 input channels 5 input channels 8 input channels 8 input channels analog comparators no no 2 2 analog comparators v ref output n/a n/a yes yes resets (and delays) por, bor, reset instruction, stack full, stack underflow (pwrt, ost) por, bor, reset instruction, stack full, stack underflow (pwrt, ost) por, bor, reset instruction, stack full, stack underflow (pwrt, ost) por, bor, reset instruction, stack full, stack underflow (pwrt, ost) programmable low-voltage detect yes yes yes yes programmable brown-out reset yes yes yes yes can module yes yes yes yes in-circuit serial programming? (icsp?) yes yes yes yes instruction set 75 instructions 75 instructions 75 instructions 75 instructions packages 28-pin spdip 28-pin soic 28-pin spdip 28-pin soic 40-pin pdip 44-pin plcc 44-pin tqfp 40-pin pdip 44-pin plcc 44-pin tqfp pic18fxx8 ds41159e-page 8 ? 2006 microchip technology inc. figure 1-1: pic18f248/258 blo ck diagram power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control osc1/clki osc2/clko/ra6 mclr v dd , v ss porta portb portc ra4/t0cki ra5/an4/ss /lvdin rb0/int0 rb4 rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt brown-out reset synchronous timer0 timer1 timer2 serial port ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0/cv ref can module timing generation 10-bit adc rb1/int1 data latch data ram up to 1536 bytes address latch address<12> 12 bank0, f bsr fsr0 fsr1 fsr2 inc/dec logic decode 4 12 4 pch pcl pclath 8 31 level stack program counter prodh 8 x 8 multiply w 8 bitop 8 8 alu<8> 8 te s t m o d e select address latch program memory up to 32 kbytes data latch 21 21 16 8 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 rom latch timer3 rb2/cantx/int2 rb3/canrx t1osi t1oso pclatu pcu precision reference band gap rb7/pgd rb5/pgm rb6/pgc pbor plvd ccp1 4x pll band gap osc2/clko/ra6 prodl data eeprom usart ? 2006 microchip technology inc. ds41159e-page 9 pic18fxx8 figure 1-2: pic18f448/458 block diagram power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control osc1/clki osc2/clko/ra6 mclr v dd , v ss porta portb portc ra4/t0cki ra5/an4/ss /lvdin rb0/int0 rb4 rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt brown-out reset comparators ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0/cv ref timing generation rb1/int1 data latch data ram up to 1536 kbytes address latch address<12> 12 bank0, f bsr fsr0 fsr1 fsr2 inc/dec logic decode 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply w 8 bitop 8 8 alu<8> 8 test mode select address latch program memory up to 32 kbytes data latch 21 21 16 8 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 rom latch portd rd0/psp0/c1in+ enhanced rb2/cantx/int2 rb3/canrx t1osi t1oso pclatu pcu precision reference band gap porte re0/an5/rd ccp rb7/pgd rb5/pgm rb6/pgc rd4/psp4/eccp1/p1a rd5/psp5/p1b rd6/psp6/p1c rd7/psp7/p1d re1/an6/wr //c1out re2/an7/cs /c2out rd1/psp1/c1in- rd2/psp2/c2in+ rd3/psp3/c2in- 4x pll band gap osc2/clko/ra6 usart synchronous timer0 timer1 timer2 serial port can module 10-bit adc timer3 pbor plvd ccp1 data eeprom usart parallel slave port pic18fxx8 ds41159e-page 10 ? 2006 microchip technology inc. table 1-2: pic18fxx8 pinout i/o descriptions pin name pin number pin type buffer type description pic18f248/258 pic18f448/458 spdip, soic pdip tqfp plcc mclr /v pp mclr v pp 11182 i p st ? master clear (input) or programming voltage (output). master clear (reset) input. this pin is an active low reset to the device. programming voltage input. nc ? ? 12, 13, 33, 34 1, 17, 28, 40 ? ? these pins should be left unconnected. osc1/clki osc1 clki 9 133014 i i cmos/st cmos oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode; otherwise, cmos. external clock source input. always associated with pin function osc1 (see osc1/ clki, osc2/clko pins). osc2/clko/ra6 osc2 clko ra6 10 14 31 15 o o i/o ? ? ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) ? 2006 microchip technology inc. ds41159e-page 11 pic18fxx8 porta is a bidirectional i/o port. ra0/an0/c vref ra0 an0 c vref 22193 i/o i o ttl analog analog digital i/o. analog input 0. comparator voltage reference output. ra1/an1 ra1 an1 33204 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref - ra2 an2 v ref - 44215 i/o i i ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 55226 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki ra4 t0cki 66237 i/o i ttl/od st digital i/o ? open-drain when configured as output. timer0 external clock input. ra5/an4/ss /lvdin ra5 an4 ss lvdin 77248 i/o i i i ttl analog st analog digital i/o. analog input 4. spi? slave select input. low-voltage detect input. ra6 see the osc2/clko/ra6 pin. table 1-2: pic18fxx8 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pic18f248/258 pic18f448/458 spdip, soic pdip tqfp plcc legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) pic18fxx8 ds41159e-page 12 ? 2006 microchip technology inc. portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0 rb0 int0 21 33 8 36 i/o i ttl st digital i/o. external interrupt 0. rb1/int1 rb1 int1 22 34 9 37 i/o i ttl st digital i/o. external interrupt 1. rb2/cantx/int2 rb2 cantx int2 23 35 10 38 i/o o i ttl ttl st digital i/o. transmit signal for can bus. external interrupt 2. rb3/canrx rb3 canrx 24 36 11 39 i/o i ttl ttl digital i/o. receive signal for can bus. rb4 25 371441i/ottl digital i/o. interrupt-on-change pin. rb5/pgm rb5 pgm 26 38 15 42 i/o i ttl st digital i/o. interrupt-on-change pin. low-voltage icsp? programming enable. rb6/pgc rb6 pgc 27 39 16 43 i/o i ttl st digital i/o. in-circuit debugger pin. interrupt-on-change pin. icsp programming clock. rb7/pgd rb7 pgd 28 40 17 44 i/o i/o ttl st digital i/o. in-circuit debugger pin. interrupt-on-change pin. icsp programming data. table 1-2: pic18fxx8 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pic18f248/258 pic18f448/458 spdip, soic pdip tqfp plcc legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) ? 2006 microchip technology inc. ds41159e-page 13 pic18fxx8 portc is a bidirectional i/o port. rc0/t1oso/t1cki rc0 t1oso t1cki 11 15 32 16 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi rc1 t1osi 12 16 35 18 i/o i st cmos digital i/o. timer1 oscillator input. rc2/ccp1 rc2 ccp1 13 17 36 19 i/o i/o st st digital i/o. capture 1 input/compare 1 output/pwm1 output. rc3/sck/scl rc3 sck scl 14 18 37 20 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi? mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi/sda rc4 sdi sda 15 23 42 25 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo rc5 sdo 16 24 43 26 i/o o st ? digital i/o. spi data out. rc6/tx/ck rc6 tx ck 17 25 44 27 i/o o i/o st ? st digital i/o. usart asynchronous transmit. usart synchronous clock (see rx/dt). rc7/rx/dt rc7 rx dt 18 26 1 29 i/o i i/o st st st digital i/o. usart asynchronous receive. usart synchronous data (see tx/ck). table 1-2: pic18fxx8 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pic18f248/258 pic18f448/458 spdip, soic pdip tqfp plcc legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) pic18fxx8 ds41159e-page 14 ? 2006 microchip technology inc. portd is a bidirectional i/o port. these pins have ttl input buffers when external memory is enabled. rd0/psp0/c1in+ rd0 psp0 c1in+ ? 193821 i/o i/o i st ttl analog digital i/o. parallel slave port data. comparator 1 input. rd1/psp1/c1in- rd1 psp1 c1in- ? 203922 i/o i/o i st ttl analog digital i/o. parallel slave port data. comparator 1 input. rd2/psp2/c2in+ rd2 psp2 c2in+ ? 214023 i/o i/o i st ttl analog digital i/o. parallel slave port data. comparator 2 input. rd3/psp3/c2in- rd3 psp3 c2in- ? 224124 i/o i/o i st ttl analog digital i/o. parallel slave port data. comparator 2 input. rd4/psp4/eccp1/ p1a rd4 psp4 eccp1 p1a ?27230 i/o i/o i/o o st ttl st ? digital i/o. parallel slave port data. eccp1 capture/compare. eccp1 pwm output a. rd5/psp5/p1b rd5 psp5 p1b ?28331 i/o i/o o st ttl ? digital i/o. parallel slave port data. eccp1 pwm output b. rd6/psp6/p1c rd6 psp6 p1c ?29432 i/o i/o o st ttl ? digital i/o. parallel slave port data. eccp1 pwm output c. rd7/psp7/p1d rd7 psp7 p1d ?30533 i/o i/o o st ttl ? digital i/o. parallel slave port data. eccp1 pwm output d. table 1-2: pic18fxx8 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pic18f248/258 pic18f448/458 spdip, soic pdip tqfp plcc legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) ? 2006 microchip technology inc. ds41159e-page 15 pic18fxx8 porte is a bidirectional i/o port. re0/an5/rd re0 an5 rd ?8259 i/o i i st analog ttl digital i/o. analog input 5. read control for parallel slave port (see wr and cs pins). re1/an6/wr /c1out re1 an6 wr c1out ?92610 i/o i i o st analog ttl analog digital i/o. analog input 6. write control for parallel slave port (see cs and rd pins). comparator 1 output. re2/an7/cs /c2out re2 an7 cs c2out ?102711 i/o i i o st analog ttl analog digital i/o. analog input 7. chip select control for parallel slave port (see rd and wr pins). comparator 2 output. v ss 19, 8 12, 31 6, 29 13, 34 ? ? ground reference for logic and i/o pins. v dd 20 11, 32 7, 28 12, 35 ? ? positive supply for logic and i/o pins. table 1-2: pic18fxx8 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pic18f248/258 pic18f448/458 spdip, soic pdip tqfp plcc legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) pic18fxx8 ds41159e-page 16 ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. ds41159e-page 17 pic18fxx8 2.0 oscillator configurations 2.1 oscillator types the pic18fxx8 can be operated in one of eight oscil- lator modes, programmable by three configuration bits (fosc2, fosc1 and fosc0). 1. lp low-power crystal 2. xt crystal/resonator 3. hs high-speed crystal/resonator 4. hs4 high-speed crystal/resonator with pll enabled 5. rc external resistor/capacitor 6. rcio external resistor/capacitor with i/o pin enabled 7. ec external clock 8. ecio external clock with i/o pin enabled 2.2 crystal oscillator/ceramic resonators in xt, lp, hs or hs4 (pll) oscillator modes, a crystal or ceramic resonator is connected to the osc1 and osc2 pins to establish oscillation. figure 2-1 shows the pin connections. an external clock source may also be connected to the osc1 pin, as shown in figure 2-3 and figure 2-4. the pic18fxx8 oscillator design requires the use of a parallel cut crystal. figure 2-1: crystal/ceramic resonator operation (hs, xt or lp osc configuration) table 2-1: ceramic resonators note: use of a series cut crystal may give a fre- quency out of the crystal manufacturer?s specifications. ranges tested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 68-100 pf 15-68 pf 15-68 pf 68-100 pf 15-68 pf 15-68 pf hs 8.0 mhz 16.0 mhz 10-68 pf 10-22 pf 10-68 pf 10-22 pf these values are for design guidance only. see notes following table 2-2. resonators used: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% all resonators used did not have built-in capacitors. note 1: see table 2-1 and table 2-2 for recommended values of c1 and c2. 2: a series resistor (r s ) may be required for at strip cut crystals. 3: r f varies with the crystal chosen. c1 (1) c2 (1) xtal osc2 osc1 r f (3) sleep to logic pic18fxx8 r s (2) internal pic18fxx8 ds41159e-page 18 ? 2006 microchip technology inc. table 2-2: capacitor selection for crystal oscillator 2.3 rc oscillator for timing insensitive applications, the ?rc? and ?rcio? device options offer additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. furthermore, the differ- ence in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 2-2 shows how the rc combination is connected. in the rc oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-2: rc oscillator mode the rcio oscillator mode functions like the rc mode, except that the osc2 pin becomes an additional general purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). osc type crystal freq cap. range c1 cap. range c2 lp 32.0 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1.0 mhz 15 pf 15 pf 4.0 mhz 15 pf 15 pf hs 4.0 mhz 15 pf 15 pf 8.0 mhz 15-33 pf 15-33 pf 20.0 mhz 15-33 pf 15-33 pf 25.0 mhz 15-33 pf 15-33 pf these values are for design guidance only. see notes on this page. crystals used 32.0 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1.0 mhz ecs ecs-10-13-1 50 ppm 4.0 mhz ecs ecs-40-20-1 50 ppm 8.0 mhz epson ca-301 8.000m-c 30 ppm 20.0 mhz epson ca-301 20.000m-c 30 ppm note 1: recommended values of c1 and c2 are identical to the ranges tested (table 2-1). 2: higher capacitance increases the stability of the oscillator but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: rs may be required in hs mode, as well as xt mode, to avoid overdriving crystals with low drive level specification. note: if the oscillator frequency divided by 4 signal is not required in the application, it is recommended to use rcio mode to save current. osc2/clko c ext r ext pic18fxx8 osc1 f osc /4 internal clock v dd v ss recommended values: 3 k r ext 100 k c ext > 20 pf ? 2006 microchip technology inc. ds41159e-page 19 pic18fxx8 2.4 external clock input the ec and ecio oscillator modes require an external clock source to be connected to the osc1 pin. the feedback device between osc1 and osc2 is turned off in these modes to save current. there is no oscilla- tor start-up time required after a power-on reset or after a recovery from sleep mode. in the ec oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-3 shows the pin connections for the ec oscillator mode. figure 2-3: external clock input operation (ec osc configuration) the ecio oscillator mode functions like the ec mode, except that the osc2 pin becomes an additional general purpose i/o pin. figure 2-4 shows the pin connections for the ecio oscillator mode. figure 2-4: external clock input operation (ecio configuration) 2.5 hs4 (pll) a phase locked loop circuit is provided as a program- mable option for users that want to multiply the frequency of the incoming crystal oscillator signal by 4. for an input clock frequency of 10 mhz, the internal clock frequency will be multiplied to 40 mhz. this is useful for customers who are concerned with emi due to high-frequency crystals. the pll can only be enabled when the oscillator configuration bits are programmed for hs mode. if they are programmed for any other mode, the pll is not enabled and the system clock will come directly from osc1. the pll is one of the modes of the fosc2:fosc0 configuration bits. the oscillator mode is specified during device programming. a pll lock timer is used to ensure that the pll has locked before device execution starts. the pll lock timer has a time-out referred to as t pll . figure 2-5: pll block diagram osc1 osc2 f osc /4 clock from ext. system pic18fxx8 osc1 i/o (osc2) clock from ext. system pic18fxx8 mux vco loop filter divide by 4 crystal osc osc2 osc1 f in f out sysclk phase comparator fosc2:fosc0 = 110 pic18fxx8 ds41159e-page 20 ? 2006 microchip technology inc. 2.6 oscillator switching feature the pic18fxx8 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low-frequency clock source. for the pic18fxx8 devices, this alternate clock source is the timer1 oscillator. if a low-frequency crystal (32 khz, for example) has been attached to the timer1 oscillator pins and the timer1 oscillator has been enabled, the device can switch to a low-power execu- tion mode. figure 2-6 shows a block diagram of the system clock sources. the clock switching feature is enabled by programming the oscillator switching enable (oscsen ) bit in configuration register, config1h, to a ? 0 ?. clock switching is disabled in an erased device. see section 12.2 ?timer1 oscillator? for further details of the timer1 oscillator and section 24.1 ?configuration bits? for configuration register details. 2.6.1 system clock switch bit the system clock source switching is performed under software control. the system clock switch bit, scs (osccon register), controls the clock switching. when the scs bit is ? 0 ?, the system clock source comes from the main oscillator selected by the fosc2:fosc0 configuration bits. when the scs bit is set, the system clock source comes from the timer1 oscillator. the scs bit is cleared on all forms of reset. figure 2-6: device clock sources register 2-1: osccon: oscillator control register note: the timer1 oscillator must be enabled to switch the system clock source. the timer1 oscillator is enabled by setting the t1oscen bit in the timer1 control regis- ter (t1con). if the timer1 oscillator is not enabled, any write to the scs bit will be ignored (scs bit forced cleared) and the main oscillator continues to be the system clock source. u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-1 ? ? ? ? ? ? ?scs bit 7 bit 0 bit 7-1 unimplemented: read as ? 0 ? bit 0 scs: system clock switch bit when oscsen configuration bit = 0 and t1oscen bit is set: 1 = switch to timer1 oscillator/clock pin 0 = use primary oscillator/clock input pin when oscsen is clear or t1oscen is clear: bit is forced clear. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 t osc 4 x pll t t 1 p t sclk clock source mux t osc /4 timer 1 oscillator t1oscen enable oscillator t1oso t1osi clock source option for other modules osc1 osc2 sleep main oscillator note: i/o pins have diode protection to v dd and v ss . ? 2006 microchip technology inc. ds41159e-page 21 pic18fxx8 2.6.2 oscillator transitions the pic18fxx8 devices contain circuitry to prevent ?glitches? when switching between oscillator sources. essentially, the circuitry waits for eight rising edges of the clock source that the processor is switching to. this ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. figure 2-7 shows a timing diagram indicating the tran- sition from the main oscillator to the timer1 oscillator. the timer1 oscillator is assumed to be running all the time. after the scs bit is set, the processor is frozen at the next occurring q1 cycle. after eight synchronization cycles are counted from the timer1 oscillator, operation resumes. no additional delays are required after the synchronization cycles. the sequence of events that takes place when switch- ing from the timer1 oscillator to the main oscillator will depend on the mode of the main oscillator. in addition to eight clock cycles of the main oscillator, additional delays may take place. if the main oscillator is configured for an external crystal (hs, xt, lp), the transition will take place after an oscillator start-up time (t ost ) has occurred. a timing diagram indicating the transition from the timer1 oscillator to the main oscillator for hs, xt and lp modes is shown in figure 2-8. figure 2-7: timing diagram for transition from os c1 to timer1 oscillator figure 2-8: timing diagram fo r transition between timer1 and osc1 (hs, xt, lp) q3 q2 q1 q4 q3 q2 osc1 internal scs (osccon<0>) program pc + 2 pc note 1: delay on internal system clock is eight oscillator cycles for synchronization. q1 t1osi q4 q1 pc + 4 q1 tscs clock counter system q2 q3 q4 q1 t dly t t 1 p t osc 2 1345678 q3 q3 q4 q1 q2 q3 q4 q1 q2 osc1 internal system scs (osccon<0>) program pc pc + 2 note 1: t ost = 1024 t osc (drawing not to scale). t1osi clock osc2 t ost q1 pc + 4 t t 1 p t osc t scs 12345678 counter pic18fxx8 ds41159e-page 22 ? 2006 microchip technology inc. if the main oscillator is configured for hs4 (pll) mode, an oscillator start-up time (t ost ) plus an additional pll time-out (t pll ) will occur. the pll time-out is typically 2 ms and allows the pll to lock to the main oscillator frequency. a timing diagram indicating the transition from the timer1 oscillator to the main oscillator for hs4 mode is shown in figure 2-9. if the main oscillator is configured in the rc, rcio, ec or ecio modes, there is no oscillator start-up time-out. operation will resume after eight cycles of the main oscillator have been counted. a timing diagram indicat- ing the transition from the timer1 oscillator to the main oscillator for rc, rcio, ec and ecio modes is shown in figure 2-10. figure 2-9: timing for transition between timer1 and osc1 (hs with pll) figure 2-10: timing for transition between timer1 and osc1 (rc, ec) q4 q1 q1 q2 q3 q4 q1 q2 osc1 internal system scs (osccon<0>) program pc pc + 2 note 1: t ost = 1024 t osc (drawing not to scale). t1osi clock t ost q3 pc + 4 t pll t osc t t 1 p t scs q4 osc2 pll clock input 1 23456 7 8 counter q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 osc1 internal system scs (osccon<0>) program pc pc + 2 note 1: rc oscillator mode assumed. pc + 4 t1osi clock osc2 q4 t t 1 p t osc t scs 12 345 67 8 counter ? 2006 microchip technology inc. ds41159e-page 23 pic18fxx8 2.7 effects of sleep mode on the on-chip oscillator when the device executes a sleep instruction, the on-chip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (q1 state). with the oscillator off, the osc1 and osc2 signals will stop oscillating. since all the transistor switching currents have been removed, sleep mode achieves the lowest current consumption of the device (only leakage currents). enabling any on-chip feature that will operate during sleep will increase the current consumed during sleep. the user can wake from sleep through external reset, watchdog timer reset or through an interrupt. 2.8 power-up delays power-up delays are controlled by two timers so that no external reset circuitry is required for most applica- tions. the delays ensure that the device is kept in reset until the device power supply and clock are stable. for additional information on reset operation, see section 3.0 ?reset? . the first timer is the power-up timer (pwrt), which optionally provides a fixed delay of t pwrt (parameter #d033) on power-up only (por and bor). the second timer is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. with the pll enabled (hs4 oscillator mode), the time- out sequence following a power-on reset is different from other oscillator modes. the time-out sequence is as follows: the pwrt time-out is invoked after a por time delay has expired, then the oscillator start-up timer (ost) is invoked. however, this is still not a sufficient amount of time to allow the pll to lock at high frequencies. the pwrt timer is used to provide an additional fixed 2 ms (nominal) to allow the pll ample time to lock to the incoming clock frequency. table 2-3: osc1 and osc2 pin states in sleep mode osc mode osc1 pin osc2 pin rc floating, external resistor should pull high at logic low rcio floating, external resistor should pull high configured as porta, bit 6 ecio floating configured as porta, bit 6 ec floating at logic low lp, xt and hs feedback inverter disabled at quiescent voltage level feedback inverter disabled at quiescent voltage level note: see table 3-1 in section 3.0 ?reset? for time-outs due to sleep and mclr reset. pic18fxx8 ds41159e-page 24 ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. ds41159e-page 25 pic18fxx8 3.0 reset the pic18fxx8 differentiates between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) watchdog timer (wdt) reset during normal operation e) programmable brown-out reset (pbor) f) reset instruction g) stack full reset h) stack underflow reset most registers are unaffected by a reset. their status is unknown on por and unchanged by all other resets. the other registers are forced to a ?reset? state on power-on reset, mclr , wdt reset, brown- out reset, mclr reset during sleep and by the reset instruction. most registers are not affected by a wdt wake-up, since this is viewed as the resumption of normal oper- ation. status bits from the rcon register, ri , to , pd , por and bor are set or cleared differently in different reset situations, as indicated in table 3-2. these bits are used in software to determine the nature of the reset. see table 3-3 for a full description of the reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 3-1. the enhanced mcu devices have a mclr noise filter in the mclr reset path. the filter will detect and ignore small pulses. a wdt reset does not drive mclr pin low. figure 3-1: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd osc1 v dd rise detect ost/pwrt on-chip rc osc (1) wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter reset enable ost (2) enable pwrt sleep note 1: this is a separate oscillator from the rc oscillator of the clki pin. 2: see table 3-1 for time-out situations. brown-out reset boren reset instruction stack pointer stack full/underflow reset wdt module pic18fxx8 ds41159e-page 26 ? 2006 microchip technology inc. 3.1 power-on reset (por) a power-on reset pulse is generated on-chip when a v dd rise is detected. to take advantage of the por circuitry, connect the mclr pin directly (or through a resistor) to v dd . this eliminates external rc compo- nents usually needed to create a power-on reset delay. a minimum rise rate for v dd is specified (refer to parameter d004). for a slow rise time, see figure 3-2. when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating condi- tions are met. brown-out reset may be used to meet the voltage start-up condition. 3.2 mclr pic18fxx8 devices have a noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. the behavior of the esd protection on the mclr pin differs from previous devices of this family. voltages applied to the pin that exceed its specification can result in both resets and current draws outside of device specification during the reset event. for this reason, microchip recommends that the mclr pin no longer be tied directly to v dd . the use of an rc network, as shown in figure 3-2, is suggested. figure 3-2: external power-on reset circuit (for slow v dd power-up) 3.3 power-up timer (pwrt) the power-up timer provides a fixed nominal time-out (parameter #33), only on power-up from the por. the power-up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrt?s time delay allows v dd to rise to an accept- able level. a configuration bit (pwrten in config2l register) is provided to enable/disable the pwrt. the power-up time delay will vary from chip to chip due to v dd , temperature and process variation. see dc parameter #33 for details. 3.4 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over (parameter #32). this additional delay ensures that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp, hs and hs4 modes and only on power-on reset or wake-up from sleep. 3.5 pll lock time-out with the pll enabled, the time-out sequence following a power-on reset is different from other oscillator modes. a portion of the power-up timer is used to pro- vide a fixed time-out that is sufficient for the pll to lock to the main oscillator frequency. this pll lock time-out (t pll ) is typically 2 ms and follows the oscillator start-up time-out (ost). 3.6 brown-out reset (bor) a configuration bit, boren, can disable (if clear/ programmed), or enable (if set), the brown-out reset circuitry. if v dd falls below parameter d005 for greater than parameter #35, the brown-out situation resets the chip. a reset may not occur if v dd falls below param- eter d005 for less than parameter #35. the chip will remain in brown-out reset until v dd rises above bv dd . the power-up timer will then be invoked and will keep the chip in reset an additional time delay (parameter #33). if v dd drops below bv dd while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initialized. once v dd rises above bv dd , the power-up timer will execute the additional time delay. note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k is recommended to make sure that the voltage drop across r does not violate the device?s electrical specification. 3: r1 = 100 to 1 k will limit any current flow- ing into mclr from external capacitor c, in the event of mclr/ v pp pin breakdown due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic18fxxx ? 2006 microchip technology inc. ds41159e-page 27 pic18fxx8 3.7 time-out sequence on power-up, the time-out sequence is as follows: first, pwrt time-out is invoked after the por time delay has expired, then ost is activated. the total time-out will vary based on oscillator configuration and the status of the pwrt. for example, in rc mode with the pwrt disabled, there will be no time-out at all. figure 3-3, figure 3-4, figure 3-5, figure 3-6 and figure 3-7 depict time-out sequences on power-up. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs will expire. bringing mclr high will begin execution immediately (figure 3-5). this is useful for testing purposes or to synchronize more than one pic18fxx8 device operating in parallel. table 3-2 shows the reset conditions for some special function registers, while table 3-3 shows the reset conditions for all registers. table 3-1: time-out in various situations register 3-1: rcon register bits and positions table 3-2: status bits, their significanc e and the initialization condition for rcon register oscillator configuration power-up (2) brown-out (2) wake-up from sleep or oscillator switch pwrten = 0 pwrten = 1 hs with pll enabled (1) 72 ms + 1024 t osc + 2 ms 1024 t osc + 2 ms 72 ms + 1024 t osc + 2 ms 1024 t osc + 2 ms hs, xt, lp 72 ms + 1024 t osc 1024 t osc 72 ms + 1024 t osc 1024 t osc ec 72 ms ? 72 ms ? external rc 72 ms ? 72 ms ? note 1: 2 ms = nominal time required for the 4x pll to lock. 2: 72 ms is the nominal power-up timer delay. r/w-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-1 ipen ? ?ri t o pd por bor bit 7 bit 0 condition program counter rcon register ri to pd por bor stkful stkunf power-on reset 0000h 0--1 110q 1 1 1 0 0 u u mclr reset during normal operation 0000h 0--0 011q u u u u u u u software reset during normal operation 0000h 0--0 011q 0 u u u u u u stack full reset during normal operation 0000h 0--0 011q u u u 1 1 u 1 stack underflow reset during normal operation 0000h 0--0 011q u u u 1 1 1 u mclr reset during sleep 0000h 0--0 011q u 1 0 u u u u wdt reset 0000h 0--0 011q u 0 1 u u u u wdt wake-up pc + 2 0--1 101q u 0 0 u u u u brown-out reset 0000h 0--1 110q 1 1 1 u 0 u u interrupt wake-up from sleep pc + 2 (1) 0--1 101q u 1 0 u u u u legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? note 1: when the wake-up is due to an interrupt and the gieh or giel bits are set, the pc is loaded with the interrupt vector (000008h or 000018h). pic18fxx8 ds41159e-page 28 ? 2006 microchip technology inc. figure 3-3: time-out sequence on power-up (mclr tied to v dd ) figure 3-4: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 3-5: time-out sequence on power-up (mclr not tied to v dd ): case 2 t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost ? 2006 microchip technology inc. ds41159e-page 29 pic18fxx8 figure 3-6: slow rise time (mclr tied to v dd ) figure 3-7: time-out sequence on por w/pll enabled (mclr tied to v dd ) v dd mclr internal por pwrt time-out ost time-out internal reset 0v 1v 5v t pwrt t ost t pwrt t ost v dd mclr iinternal por pwrt time-out ost time-out internal reset pll time-out t pll note: t ost = 1024 clock cycles. t pll 2 ms max. first three stages of the pwrt timer. pic18fxx8 ds41159e-page 30 ? 2006 microchip technology inc. table 3-3: initialization co nditions for all registers register applicable devices power-on reset, brown-out reset mclr reset wdt reset reset instruction stack resets wake-up via wdt or interrupt tosu pic18f2x8 pic18f4x8 ---0 0000 ---0 0000 ---0 uuuu (3) tosh pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu (3) tosl pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu (3) stkptr pic18f2x8 pic18f4x8 00-0 0000 uu-0 0000 uu-u uuuu (3) pclatu pic18f2x8 pic18f4x8 ---0 0000 ---0 0000 ---u uuuu pclath pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu pcl pic18f2x8 pic18f4x8 0000 0000 0000 0000 pc + 2 (2) tblptru pic18f2x8 pic18f4x8 --00 0000 --00 0000 --uu uuuu tblptrh pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu tblptrl pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu tablat pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu prodh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu prodl pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu intcon pic18f2x8 pic18f4x8 0000 000x 0000 000u uuuu uuuu (1) intcon2 pic18f2x8 pic18f4x8 111- -1-1 111- -1-1 uuu- -u-u (1) intcon3 pic18f2x8 pic18f4x8 11-0 0-00 11-0 0-00 uu-u u-uu (1) indf0 pic18f2x8 pic18f4x8 n/a n/a n/a postinc0 pic18f2x8 pic18f4x8 n/a n/a n/a postdec0 pic18f2x8 pic18f4x8 n/a n/a n/a preinc0 pic18f2x8 pic18f4x8 n/a n/a n/a plusw0 pic18f2x8 pic18f4x8 n/a n/a n/a fsr0h pic18f2x8 pic18f4x8 ---- xxxx ---- uuuu ---- uuuu fsr0l pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu wreg pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu indf1 pic18f2x8 pic18f4x8 n/a n/a n/a postinc1 pic18f2x8 pic18f4x8 n/a n/a n/a postdec1 pic18f2x8 pic18f4x8 n/a n/a n/a preinc1 pic18f2x8 pic18f4x8 n/a n/a n/a plusw1 pic18f2x8 pic18f4x8 n/a n/a n/a legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ?. 6: values for canstat also apply to its other instances (canstatro1 through canstatro4). ? 2006 microchip technology inc. ds41159e-page 31 pic18fxx8 fsr1h pic18f2x8 pic18f4x8 ---- xxxx ---- uuuu ---- uuuu fsr1l pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu bsr pic18f2x8 pic18f4x8 ---- 0000 ---- 0000 ---- uuuu indf2 pic18f2x8 pic18f4x8 n/a n/a n/a postinc2 pic18f2x8 pic18f4x8 n/a n/a n/a postdec2 pic18f2x8 pic18f4x8 n/a n/a n/a preinc2 pic18f2x8 pic18f4x8 n/a n/a n/a plusw2 pic18f2x8 pic18f4x8 n/a n/a n/a fsr2h pic18f2x8 pic18f4x8 ---- xxxx ---- uuuu ---- uuuu fsr2l pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu status pic18f2x8 pic18f4x8 ---x xxxx ---u uuuu ---u uuuu tmr0h pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu tmr0l pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu t0con pic18f2x8 pic18f4x8 1111 1111 1111 1111 uuuu uuuu osccon pic18f2x8 pic18f4x8 ---- ---0 ---- ---0 ---- ---u lvdcon pic18f2x8 pic18f4x8 --00 0101 --00 0101 --uu uuuu wdtcon pic18f2x8 pic18f4x8 ---- ---0 ---- ---0 ---- ---u rcon (4) pic18f2x8 pic18f4x8 0--1 110q 0--0 011q 0--1 101q tmr1h pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu tmr1l pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu t1con pic18f2x8 pic18f4x8 0-00 0000 u-uu uuuu u-uu uuuu tmr2 pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu pr2 pic18f2x8 pic18f4x8 1111 1111 1111 1111 1111 1111 t2con pic18f2x8 pic18f4x8 -000 0000 -000 0000 -uuu uuuu sspbuf pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu sspadd pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu sspstat pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu sspcon1 pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu sspcon2 pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu adresh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu adresl pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu adcon0 pic18f2x8 pic18f4x8 0000 00-0 0000 00-0 uuuu uu-u table 3-3: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr reset wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ?. 6: values for canstat also apply to its other instances (canstatro1 through canstatro4). pic18fxx8 ds41159e-page 32 ? 2006 microchip technology inc. adcon1 pic18f2x8 pic18f4x8 00-- 0000 00-- 0000 uu-- uuuu ccpr1h pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu ccpr1l pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu ccp1con pic18f2x8 pic18f4x8 --00 0000 --00 0000 --uu uuuu eccpr1h pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu eccpr1l pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu eccp1con pic18f2x8 pic18f4x8 0000 0000 0000 0000 0000 0000 eccp1del pic18f2x8 pic18f4x8 0000 0000 0000 0000 0000 0000 eccpas pic18f2x8 pic18f4x8 0000 0000 0000 0000 0000 0000 cvrcon pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu cmcon pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu tmr3h pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu tmr3l pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu t3con pic18f2x8 pic18f4x8 0000 0000 uuuu uuuu uuuu uuuu spbrg pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu rcreg pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu txreg pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu txsta pic18f2x8 pic18f4x8 0000 -010 0000 -010 uuuu -uuu rcsta pic18f2x8 pic18f4x8 0000 000x 0000 000u uuuu uuuu eeadr pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu eedata pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu eecon2 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu eecon1 pic18f2x8 pic18f4x8 xx-0 x000 uu-0 u000 uu-0 u000 ipr3 pic18f2x8 pic18f4x8 1111 1111 1111 1111 uuuu uuuu pir3 pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu pie3 pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu ipr2 pic18f2x8 pic18f4x8 -1-1 1111 -1-1 1111 -u-u uuuu pir2 pic18f2x8 pic18f4x8 -0-0 0000 -0-0 0000 -u-u uuuu (1) pie2 pic18f2x8 pic18f4x8 -0-0 0000 -0-0 0000 -u-u uuuu ipr1 pic18f2x8 pic18f4x8 1111 1111 1111 1111 uuuu uuuu pir1 pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu (1) pie1 pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu table 3-3: initialization condition s for all registers (continued) register applicable devices power-on reset, brown-out reset mclr reset wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ?. 6: values for canstat also apply to its other instances (canstatro1 through canstatro4). ? 2006 microchip technology inc. ds41159e-page 33 pic18fxx8 trise pic18f2x8 pic18f4x8 0000 -111 0000 -111 uuuu -uuu trisd pic18f2x8 pic18f4x8 1111 1111 1111 1111 uuuu uuuu trisc pic18f2x8 pic18f4x8 1111 1111 1111 1111 uuuu uuuu trisb pic18f2x8 pic18f4x8 1111 1111 1111 1111 uuuu uuuu trisa (5) pic18f2x8 pic18f4x8 -111 1111 (5) -111 1111 (5) -uuu uuuu (5) late pic18f2x8 pic18f4x8 ---- -xxx ---- -uuu ---- -uuu latd pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu latc pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu latb pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu lata (5) pic18f2x8 pic18f4x8 -xxx xxxx (5) -uuu uuuu (5) -uuu uuuu (5) porte pic18f2x8 pic18f4x8 ---- -xxx ---- -000 ---- -uuu portd pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu portc pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu portb pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu porta (5) pic18f2x8 pic18f4x8 -x0x 0000 ( 5) -u0u 0000 (5) -uuu uuuu (5) txerrcnt pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu rxerrcnt pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu comstat pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu ciocon pic18f2x8 pic18f4x8 --00 ---- --00 ---- --uu ---- brgcon3 pic18f2x8 pic18f4x8 -0-- -000 -0-- -000 -u-- -uuu brgcon2 pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu brgcon1 pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu cancon pic18f2x8 pic18f4x8 xxxx xxx- uuuu uuu- uuuu uuu- canstat (6) pic18f2x8 pic18f4x8 xxx- xxx- uuu- uuu- uuu- uuu- rxb0d7 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb0d6 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb0d5 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb0d4 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb0d3 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb0d2 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb0d1 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb0d0 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu table 3-3: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr reset wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ?. 6: values for canstat also apply to its other instances (canstatro1 through canstatro4). pic18fxx8 ds41159e-page 34 ? 2006 microchip technology inc. rxb0dlc pic18f2x8 pic18f4x8 -xxx xxxx -uuu uuuu -uuu uuuu rxb0eidl pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb0eidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb0sidl pic18f2x8 pic18f4x8 xxxx x-xx uuuu u-uu uuuu u-uu rxb0sidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb0con pic18f2x8 pic18f4x8 000- 0000 000- 0000 uuu- uuuu rxb1d7 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb1d6 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb1d5 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb1d4 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb1d3 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb1d2 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb1d1 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb1d0 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb1dlc pic18f2x8 pic18f4x8 -xxx xxxx -uuu uuuu -uuu uuuu rxb1eidl pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb1eidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb1sidl pic18f2x8 pic18f4x8 xxxx x-xx uuuu u-uu uuuu u-uu rxb1sidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxb1con pic18f2x8 pic18f4x8 000- 0000 000- 0000 uuu- uuuu txb0d7 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb0d6 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb0d5 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb0d4 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb0d3 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb0d2 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb0d1 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb0d0 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb0dlc pic18f2x8 pic18f4x8 -x-- xxxx -u-- uuuu -u-- uuuu txb0eidl pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb0eidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb0sidl pic18f2x8 pic18f4x8 xxx- x-xx uuu- u-uu uuu- u-uu table 3-3: initialization condition s for all registers (continued) register applicable devices power-on reset, brown-out reset mclr reset wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ?. 6: values for canstat also apply to its other instances (canstatro1 through canstatro4). ? 2006 microchip technology inc. ds41159e-page 35 pic18fxx8 txb0sidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb0con pic18f2x8 pic18f4x8 -000 0-00 -000 0-00 -uuu u-uu txb1d7 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb1d6 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb1d5 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb1d4 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb1d3 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb1d2 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb1d1 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb1d0 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb1dlc pic18f2x8 pic18f4x8 -x-- xxxx -u-- uuuu -u-- uuuu txb1eidl pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb1eidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb1sidl pic18f2x8 pic18f4x8 xxx- x-xx uuu- u-uu uuu- u-uu txb1sidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb1con pic18f2x8 pic18f4x8 0000 0000 0000 0000 uuuu uuuu txb2d7 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb2d6 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb2d5 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb2d4 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb2d3 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb2d2 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb2d1 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb2d0 pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb2dlc pic18f2x8 pic18f4x8 -x-- xxxx -u-- uuuu -u-- uuuu txb2eidl pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb2eidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb2sidl pic18f2x8 pic18f4x8 xxx- x-xx uuu- u-uu uuu- u-uu txb2sidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu txb2con pic18f2x8 pic18f4x8 -000 0-00 -000 0-00 -uuu u-uu rxm1eidl pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxm1eidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu table 3-3: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr reset wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ?. 6: values for canstat also apply to its other instances (canstatro1 through canstatro4). pic18fxx8 ds41159e-page 36 ? 2006 microchip technology inc. rxm1sidl pic18f2x8 pic18f4x8 xxx- --xx uuu- --uu uuu- --uu rxm1sidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxm0eidl pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxm0eidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxm0sidl pic18f2x8 pic18f4x8 xxx- --xx uuu- --uu uuu- --uu rxm0sidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf5eidl pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf5eidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf5sidl pic18f2x8 pic18f4x8 xxx- x-xx uuu- u-uu uuu- u-uu rxf5sidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf4eidl pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf4eidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf4sidl pic18f2x8 pic18f4x8 xxx- x-xx uuu- u-uu uuu- u-uu rxf4sidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf3eidl pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf3eidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf3sidl pic18f2x8 pic18f4x8 xxx- x-xx uuu- u-uu uuu- u-uu rxf3sidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf2eidl pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf2eidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf2sidl pic18f2x8 pic18f4x8 xxx- x-xx uuu- u-uu uuu- u-uu rxf2sidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf1eidl pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf1eidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf1sidl pic18f2x8 pic18f4x8 xxx- x-xx uuu- u-uu uuu- u-uu rxf1sidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf0eidl pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf0eidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu rxf0sidl pic18f2x8 pic18f4x8 xxx- x-xx uuu- u-uu uuu- u-uu rxf0sidh pic18f2x8 pic18f4x8 xxxx xxxx uuuu uuuu uuuu uuuu table 3-3: initialization condition s for all registers (continued) register applicable devices power-on reset, brown-out reset mclr reset wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ?. 6: values for canstat also apply to its other instances (canstatro1 through canstatro4). ? 2006 microchip technology inc. ds41159e-page 37 pic18fxx8 4.0 memory organization there are three memory blocks in enhanced mcu devices. these memory blocks are: ? enhanced flash program memory ? data memory ? eeprom data memory data and program memory use separate busses, which allows concurrent access of these blocks. additional detailed information on data eeprom and flash program memory is provided in section 5.0 ?data eeprom memory? and section 6.0 ?flash program memory? , respectively. 4.1 program memory organization the pic18f258/458 devices have a 21-bit program counter that is capable of addressing a 2-mbyte program memory space. the reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. figure 4-1: program memory map and stack for pic18f248/448 figure 4-1 shows the diagram for program memory map and stack for the pic18f248 and pic18f448. figure 4-2 shows the diagram for the program memory map and stack for the pic18f258 and pic18f458. 4.1.1 internal program memory operation the pic18f258 and the pic18f458 have 32 kbytes of internal enhanced flash program memory. this means that the pic18f258 and the pic18f458 can store up to 16k of single-word instructions. the pic18f248 and pic18f448 have 16 kbytes of enhanced flash program memory. this translates into 8192 single-word instructions, which can be stored in the program memory. accessing a location between the physically implemented memory and the 2-mbyte address will cause a read of all ? 0 ?s (a nop instruction). figure 4-2: program memory map and stack for pic18f258/458 pc<20:0> stack level 1 ? stack level 31 reset vector low priority interrupt vector ? ? 21 0000h 0018h on-chip program memory high priority interrupt vector 0008h user memory space 1fffffh 4000h 3fffh read ? 0 ? 200000h call,rcall,return retfie,retlw pc<20:0> stack level 1 stack level 31 reset vector low priority interrupt vector call,rcall,return retfie,retlw 21 0000h 0018h 8000h 7fffh on-chip program memory high priority interrupt vector 0008h user memory space read ? 0 ? 1fffffh 200000h ? ? ? pic18fxx8 ds41159e-page 38 ? 2006 microchip technology inc. 4.2 return address stack the return address stack allows any combination of up to 31 program calls and interrupts to occur. the pc (program counter) is pushed onto the stack when a push , call or rcall instruction is executed, or an interrupt is acknowledged. the pc value is pulled off the stack on a return, retlw or a retfie instruc- tion. pclatu and pclath are not affected by any of the return instructions. the stack operates as a 31-word by 21-bit stack memory and a 5-bit stack pointer register, with the stack pointer initialized to 00000b after all resets. there is no ram associated with stack pointer 00000b. this is only a reset value. during a call type instruction, causing a push onto the stack, the stack pointer is first incremented and the ram location pointed to by the stack pointer is written with the con- tents of the pc. during a return type instruction, causing a pop from the stack, the contents of the ram location indicated by the stkptr are transferred to the pc and then the stack pointer is decremented. the stack space is not part of either program or data space. the stack pointer is readable and writable and the data on the top of the stack is readable and writable through sfr registers. status bits indicate if the stack pointer is at or beyond the 31 levels provided. 4.2.1 top-of-stack access the top of the stack is readable and writable. three register locations, tosu, tosh and tosl allow access to the contents of the stack location indicated by the stkptr register. this allows users to implement a software stack, if necessary. after a call , rcall or interrupt, the software can read the pushed value by reading the tosu, tosh and tosl registers. these values can be placed on a user defined software stack. at return time, the software can replace the tosu, tosh and tosl and do a return. the user should disable the global interrupt enable bits during this time to prevent inadvertent stack operations. 4.2.2 return stack pointer (stkptr) the stkptr register contains the stack pointer value, the stkful (stack full) status bit and the stkunf (stack underflow) status bits. register 4-1 shows the stkptr register. the value of the stack pointer can be 0 through 31. the stack pointer increments when val- ues are pushed onto the stack and decrements when values are popped off the stack. at reset, the stack pointer value will be ? 0 ?. the user may read and write the stack pointer value. this feature can be used by a real-time operating system for return stack maintenance. after the pc is pushed onto the stack 31 times (without popping any values off the stack), the stkful bit is set. the stkful bit can only be cleared in software or by a por. the action that takes place when the stack becomes full depends on the state of the stvren (stack over- flow reset enable) configuration bit. refer to section 21.0 ?comparator module? for a description of the device configuration bits. if stvren is set (default), the 31st push will push the (pc + 2) value onto the stack, set the stkful bit and reset the device. the stkful bit will remain set and the stack pointer will be set to ? 0 ?. if stvren is cleared, the stkful bit will be set on the 31st push and the stack pointer will increment to 31. the 32nd push will overwrite the 31st push (and so on), while stkptr remains at 31. when the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the pc and sets the stkunf bit, while the stack pointer remains at ? 0 ?. the stkunf bit will remain set until cleared in software or a por occurs. note: returning a value of zero to the pc on an underflow has the effect of vectoring the program to the reset vector, where the stack conditions can be verified and appropriate actions can be taken. ? 2006 microchip technology inc. ds41159e-page 39 pic18fxx8 register 4-1: stkptr: stack pointer register figure 4-3: return address stack and associated registers r/c-0 r/c-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stkful stkunf ? sp4 sp3 sp2 sp1 sp0 bit 7 bit 0 bit 7 stkful : stack full flag bit 1 = stack became full or overflowed 0 = stack has not become full or overflowed bit 6 stkunf : stack underflow flag bit 1 = stack underflow occurred 0 = stack underflow did not occur bit 5 unimplemented : read as ? 0 ? bit 4-0 sp4:sp0 : stack pointer location bits note: bit 7 and bit 6 need to be cleared following a stack underflow or a stack overflow. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared c = clearable bit 00011 001a34h 11111 11110 11101 00010 00001 00000 (1) 00010 return address stack top-of-stack 000d58h tosl tosh tosu 34h 1ah 00h stkptr<4:0> 000000h note 1: no ram associated with this address; always maintained ? 0 ?s. pic18fxx8 ds41159e-page 40 ? 2006 microchip technology inc. 4.2.3 push and pop instructions since the top-of-stack (tos) is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execu- tion, is a desirable option. to push the current pc value onto the stack, a push instruction can be executed. this will increment the stack pointer and load the current pc value onto the stack. tosu, tosh and tosl can then be modified to place a return address on the stack. the pop instruction discards the current tos by decre- menting the stack pointer. the previous value pushed onto the stack then becomes the tos value. 4.2.4 stack full/underflow resets these resets are enabled by programming the stvren configuration bit. when the stvren bit is disabled, a full or underflow condition will set the appro- priate stkful or stkunf bit, but not cause a device reset. when the stvren bit is enabled, a full or underflow condition will set the appropriate stkful or stkunf bit and then cause a device reset. the stkful or stkunf bits are only cleared by the user software or a por. 4.3 fast register stack a ?fast return? option is available for interrupts and calls. a fast register stack is provided for the status, wreg and bsr registers and is only one layer in depth. the stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. the values in the fast register stack are then loaded back into the working registers if the fast return instruction is used to return from the interrupt. a low or high priority interrupt source will push values into the stack registers. if both low and high priority interrupts are enabled, the stack registers cannot be used reliably for low priority interrupts. if a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. if high priority interrupts are not disabled during low priority interrupts, users must save the key registers in software during a low priority interrupt. if no interrupts are used, the fast register stack can be used to restore the status, wreg and bsr registers at the end of a subroutine call. to use the fast register stack for a subroutine call, a fast call instruction must be executed. example 4-1 shows a source code example that uses the fast register stack. example 4-1: fast register stack code example 4.4 pcl, pclath and pclatu the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 21 bits wide. the low byte is called the pcl register. this reg- ister is readable and writable. the high byte is called the pch register. this register contains the pc<15:8> bits and is not directly readable or writable. updates to the pch register may be performed through the pclath register. the upper byte is called pcu. this register contains the pc<20:16> bits and is not directly readable or writable. updates to the pcu register may be performed through the pclatu register. the pc addresses bytes in the program memory. to prevent the pc from becoming misaligned with word instructions, the lsb of pcl is fixed to a value of ? 0 ?. the pc increments by 2 to address sequential instructions in the program memory. the call, rcall, goto and program branch instructions write to the program counter directly. for these instructions, the contents of pclath and pclatu are not transferred to the program counter. the contents of pclath and pclatu will be transferred to the program counter by an operation that writes pcl. similarly, the upper two bytes of the program counter will be transferred to pclath and pclatu by an operation that reads pcl. this is useful for computed offsets to the pc (see section 4.8.1 ?computed goto? ). call sub1, fast ;status, wreg, bsr ;saved in fast register ;stack ? ? sub1 ? ? ? return fast ;restore values saved ;in fast register stack ? 2006 microchip technology inc. ds41159e-page 41 pic18fxx8 4.5 clocking scheme/instruction cycle the clock input (from osc1) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3 and q4. internally, the program counter (pc) is incremented every q1, the instruction is fetched from the program memory and latched into the instruction register in q4. the instruc- tion is decoded and executed during the following q1 through q4. the clocks and instruction execution flow are shown in figure 4-4. figure 4-4: clock/instruct ion cycle 4.6 instruction flow/pipelining an ?instruction cycle? consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ), two cycles are required to complete the instruction (example 4-2). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the ?instruction register? (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). 4.7 instructions in program memory the program memory is addressed in bytes. instruc- tions are stored as two bytes or four bytes in program memory. the least significant byte of an instruction word is always stored in a program memory location with an even address (lsb = 0 ). figure 4-3 shows an example of how instruction words are stored in the program memory. to maintain alignment with instruc- tion boundaries, the pc increments in steps of 2 and the lsb will always read ? 0 ? (see section 4.4 ?pcl, pclath and pclatu? ). the call and goto instructions have an absolute program memory address embedded into the instruc- tion. since instructions are always stored on word boundaries, the data contained in the instruction is a word address. the word address is written to pc<20:1>, which accesses the desired byte address in program memory. instruction #2 in example 4-3 shows how the instruction ? goto 000006h ? is encoded in the program memory. program branch instructions that encode a relative address offset operate in the same manner. the offset value stored in a br anch instruction represents the number of single-word instructions by which the pc will be offset. section 25.0 ?instruction set summary? provides further details of the instruction set. q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clko (rc mode) pc pc + 2 pc + 4 fetch inst (pc) execute inst (pc ? 2) fetch inst (pc + 2) execute inst (pc) fetch inst (pc + 4) execute inst (pc + 2) internal phase clock pic18fxx8 ds41159e-page 42 ? 2006 microchip technology inc. example 4-2: instruction pipeline flow example 4-3: instructions in program memory note: all instructions are single cycle, except for any program branches. these take two cycles, since the fetch instruction is ?flushed? from the pipeline while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. bra sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush 5. instruction @ address sub_1 fetch sub_1 execute sub_1 instruction opcode memory address ? 000007h movlw 055h 0e55h 55h 000008h 0eh 000009h goto 000006h 0ef03h, 0f000h 03h 00000ah 0efh 00000bh 00h 00000ch 0f0h 00000dh movff 123h, 456h 0c123h, 0f456h 23h 00000eh 0c1h 00000fh 56h 000010h 0f4h 000011h ? 000012h ? 2006 microchip technology inc. ds41159e-page 43 pic18fxx8 4.7.1 two-word instructions the pic18fxx8 devices have 4 two-word instructions: movff, call, goto and lfsr . the 4 most signifi- cant bits of the second word are set to ? 1 ?s and indicate a special nop instruction. the lower 12 bits of the second word contain the data to be used by the instruction. if the first word of the instruction is executed, the data in the second word is accessed. if the second word of the instruction is executed by itself (first word was skipped), it will execute as a nop . this action is necessary when the two-word instruction is preceded by a conditional instruction that changes the pc. a program example that demonstrates this concept is shown in example 4-4. refer to section 25.0 ?instruction set summary? for further details of the instruction set. 4.8 look-up tables look-up tables are implemented two ways. these are: ? computed goto ? table reads 4.8.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). a look-up table can be formed with an addwf pcl instruction and a group of retlw 0xnn instructions. wreg is loaded with an offset into the table before executing a call to that table. the first instruction of the called routine is the addwf pcl instruction. the next instruction executed will be one of the retlw 0xnn instructions that returns the value 0xnn to the calling function. the offset value (value in wreg) specifies the number of bytes that the program counter should advance. in this method, only one data byte may be stored in each instruction location and room on the return address stack is required. 4.8.2 table reads/table writes a better method of storing data in program memory allows 2 bytes of data to be stored in each instruction location. look-up table data may be stored as 2 bytes per program word by using table reads and writes. the table pointer (tblptr) specifies the byte address and the table latch (tablat) contains the data that is read from, or written to, program memory. data is transferred to/from program memory, one byte at a time. a description of the table read/table write operation is shown in section 6.1 ?table reads and table writes? . example 4-4: two-word instructions note 1: the lsb of pcl is fixed to a value of ? 0 ?. hence, computed goto to an odd address is not possible. 2: the addwf pcl instruction does not update pclath/pclatu. a read opera- tion on pcl must be performed to update pclath and pclatu. case 1: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; no, execute 2-word instruction 1111 0100 0101 0110 ; 2nd operand holds address of reg2 0010 0100 0000 0000 addwf reg3 ; continue code case 2: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; yes 1111 0100 0101 0110 ; 2nd operand becomes nop 0010 0100 0000 0000 addwf reg3 ; continue code pic18fxx8 ds41159e-page 44 ? 2006 microchip technology inc. 4.9 data memory organization the data memory is implemented as static ram. each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. figure 4-6 shows the data memory organization for the pic18fxx8 devices. the data memory map is divided into as many as 16 banks that contain 256 bytes each. the lower 4 bits of the bank select register (bsr<3:0>) select which bank will be accessed. the upper 4 bits for the bsr are not implemented. the data memory contains special function registers (sfrs) and general purpose registers (gprs). the sfrs are used for control and status of the controller and peripheral functions, while gprs are used for data storage and scratchpad operations in the user?s appli- cation. the sfrs start at the last location of bank 15 (fffh) and grow downwards. gprs start at the first location of bank 0 and grow upwards. any read of an unimplemented location will read as ? 0 ?s. the entire data memory may be accessed directly or indirectly. direct addressing may require the use of the bsr register. indirect addressing requires the use of the file select register (fsr). each fsr holds a 12-bit address value that can be used to access any location in the data memory map without banking. the instruction set and architecture allow operations across all banks. this may be accomplished by indirect addressing or by the use of the movff instruction. the movff instruction is a two-word/two-cycle instruction, that moves a value from one register to another. to ensure that commonly used registers (sfrs and select gprs) can be accessed in a single cycle, regardless of the current bsr values, an access bank is implemented. a segment of bank 0 and a segment of bank 15 comprise the access ram. section 4.10 ?access bank? provides a detailed description of the access ram. 4.9.1 general purpose register file the register file can be accessed either directly or indirectly. indirect addressing operates through the file select registers (fsr). the operation of indirect addressing is shown in section 4.12 ?indirect addressing, indf and fsr registers? . enhanced mcu devices may have banked memory in the gpr area. gprs are not initialized by a power-on reset and are unchanged on all other resets. data ram is available for use as gpr registers by all instructions. bank 15 (f00h to fffh) contains sfrs. all other banks of data memory contain gpr registers, starting with bank 0. 4.9.2 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. a list of these registers is given in table 4-1. the sfrs can be classified into two sets: those asso- ciated with the ?core? function and those related to the peripheral functions. those registers related to the ?core? are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. the sfrs are typically distributed among the peripherals whose functions they control. the unused sfr locations will be unimplemented and read as ? 0 ?s. see table 4-1 for addresses for the sfrs. ? 2006 microchip technology inc. ds41159e-page 45 pic18fxx8 figure 4-5: data memory map for pic18f248/448 bank 0 bank 1 bank 14 bank 15 data memory map bsr<3:0> = 0000 = 0001 = 1111 060h 05fh f60h fffh 00h 5fh 60h ffh access bank f5fh f00h effh 1ffh 100h 0ffh 000h access ram ffh 00h ffh 00h ffh 00h gpr gpr sfr unused access bank high access bank low bank 3 to 200h unused read ?00h? = 1110 = 0011 when a = 0 , the bsr is ignored and the access bank is used. the first 96 bytes are general purpose ram (from bank 0). the next 160 bytes are special function registers (from bank 15). when a = 1 , the bsr is used to specify the ram location that the instruction uses. gpr ffh 00h 300h (sfr) (gpr) bank 2 = 0010 pic18fxx8 ds41159e-page 46 ? 2006 microchip technology inc. figure 4-6: data memory map for pic18f258/458 bank 0 bank 1 bank 14 bank 15 data memory map bsr<3:0> = 0000 = 0001 = 1110 = 1111 060h 05fh f60h fffh 00h 5fh 60h ffh access bank bank 4 bank 3 bank 2 f5fh f00h effh 3ffh 300h 2ffh 200h 1ffh 100h 0ffh 000h = 0110 = 0101 = 0011 = 0010 access ram ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h gpr gpr gpr gpr sfr sfr access bank high access bank low bank 5 gpr gpr bank 6 to 4ffh 400h 5ffh 500h 600h unused read ?00h? = 0100 (sfr) when a = 0 , the bsr is ignored and the access bank is used. the first 96 bytes are general purpose ram (from bank 0). the next 160 bytes are special function registers (from bank 15). when a = 1 , the bsr is used to specify the ram location that the instruction uses. (gpr) ? 2006 microchip technology inc. ds41159e-page 47 pic18fxx8 table 4-1: special function register map address name address name address name address name fffh tosu fdfh indf2 (2) fbfh ccpr1h f9fh ipr1 ffeh tosh fdeh postinc2 (2) fbeh ccpr1l f9eh pir1 ffdh tosl fddh postdec2 (2) fbdh ccp1con f9dh pie1 ffch stkptr fdch preinc2 (2) fbch eccpr1h (5) f9ch ? ffbh pclatu fdbh plusw2 (2) fbbh eccpr1l (5) f9bh ? ffah pclath fdah fsr2h fbah eccp1con (5) f9ah ? ff9h pcl fd9h fsr2l fb9h ? f99h ? ff8h tblptru fd8h status fb8h ? f98h ? ff7h tblptrh fd7h tmr0h fb7h eccp1del (5) f97h ? ff6h tblptrl fd6h tmr0l fb6h eccpas (5) f96h trise (5) ff5h tablat fd5h t0con fb5h cvrcon (5) f95h trisd (5) ff4h prodh fd4h ? fb4h cmcon (5) f94h trisc ff3h prodl fd3h osccon fb3h tmr3h f93h trisb ff2h intcon fd2h lvdcon fb2h tmr3l f92h trisa ff1h intcon2 fd1h wdtcon fb1h t3con f91h ? ff0h intcon3 fd0h rcon fb0h ? f90h ? fefh indf0 (2) fcfh tmr1h fafh spbrg f8fh ? feeh postinc0 (2) fceh tmr1l faeh rcreg f8eh ? fedh postdec0 (2) fcdh t1con fadh txreg f8dh late (5) fech preinc0 (2) fcch tmr2 fach txsta f8ch latd (5) febh plusw0 (2) fcbh pr2 fabh rcsta f8bh latc feah fsr0h fcah t2con faah ? f8ah latb fe9h fsr0l fc9h sspbuf fa9h eeadr f89h lata fe8h wreg fc8h sspadd fa8h eedata f88h ? fe7h indf1 (2) fc7h sspstat fa7h eecon2 f87h ? fe6h postinc1 (2) fc6h sspcon1 fa6h eecon1 f86h ? fe5h postdec1 (2) fc5h sspcon2 fa5h ipr3 f85h ? fe4h preinc1 (2) fc4h adresh fa4h pir3 f84h porte (5) fe3h plusw1 (2) fc3h adresl fa3h pie3 f83h portd (5) fe2h fsr1h fc2h adcon0 fa2h ipr2 f82h portc fe1h fsr1l fc1h adcon1 fa1h pir2 f81h portb fe0h bsr fc0h ? fa0h pie2 f80h porta note 1: unimplemented registers are read as ? 0 ?. 2: this is not a physical register. 3: contents of register are dependent on win2:win0 bits in the cancon register. 4: canstat register is repeated in these locations to simplify application firmware. unique names are given for each instance of the canstat register due to the microchip header file requirement. 5: these registers are not implemented on the pic18f248 and pic18f258. pic18fxx8 ds41159e-page 48 ? 2006 microchip technology inc. f7fh ? f5fh ? f3fh ? f1fh rxm1eidl f7eh ? f5eh canstatro1 (4) f3eh canstatro3 (4) f1eh rxm1eidh f7dh ? f5dh rxb1d7 f3dh txb1d7 f1dh rxm1sidl f7ch ? f5ch rxb1d6 f3ch txb1d6 f1ch rxm1sidh f7bh ? f5bh rxb1d5 f3bh txb1d5 f1bh rxm0eidl f7ah ? f5ah rxb1d4 f3ah txb1d4 f1ah rxm0eidh f79h ? f59h rxb1d3 f39h txb1d3 f19h rxm0sidl f78h ? f58h rxb1d2 f38h txb1d2 f18h rxm0sidh f77h ? f57h rxb1d1 f37h txb1d1 f17h rxf5eidl f76h txerrcnt f56h rxb1d0 f36h txb1d0 f16h rxf5eidh f75h rxerrcnt f55h rxb1dlc f35h txb1dlc f15h rxf5sidl f74h comstat f54h rxb1eidl f34h txb1eidl f14h rxf5sidh f73h ciocon f53h rxb1eidh f33h txb1eidh f13h rxf4eidl f72h brgcon3 f52h rxb1sidl f32h txb1sidl f12h rxf4eidh f71h brgcon2 f51h rxb1sidh f31h txb1sidh f11h rxf4sidl f70h brgcon1 f50h rxb1con f30h txb1con f10h rxf4sidh f6fh cancon f4fh ? f2fh ? f0fh rxf3eidl f6eh canstat f4eh canstatro2 (4) f2eh canstatro4 (4) f0eh rxf3eidh f6dh rxb0d7 (3) f4dh txb0d7 f2dh txb2d7 f0dh rxf3sidl f6ch rxb0d6 (3) f4ch txb0d6 f2ch txb2d6 f0ch rxf3sidh f6bh rxb0d5 (3) f4bh txb0d5 f2bh txb2d5 f0bh rxf2eidl f6ah rxb0d4 (3) f4ah txb0d4 f2ah txb2d4 f0ah rxf2eidh f69h rxb0d3 (3) f49h txb0d3 f29h txb2d3 f09h rxf2sidl f68h rxb0d2 (3) f48h txb0d2 f28h txb2d2 f08h rxf2sidh f67h rxb0d1 (3) f47h txb0d1 f27h txb2d1 f07h rxf1eidl f66h rxb0d0 (3) f46h txb0d0 f26h txb2d0 f06h rxf1eidh f65h rxb0dlc (3) f45h txb0dlc f25h txb2dlc f05h rxf1sidl f64h rxb0eidl (3) f44h txb0eidl f24h txb2eidl f04h rxf1sidh f63h rxb0eidh (3) f43h txb0eidh f23h txb2eidh f03h rxf0eidl f62h rxb0sidl (3) f42h txb0sidl f22h txb2sidl f02h rxf0eidh f61h rxb0sidh (3) f41h txb0sidh f21h txb2sidh f01h rxf0sidl f60h rxb0con (3) f40h txb0con f20h txb2con f00h rxf0sidh note: shaded registers are available in bank 15, while the rest are in access bank low. table 4-1: special function register map (continued) address name address name address name address name note 1: unimplemented registers are read as ? 0 ?. 2: this is not a physical register. 3: contents of register are dependent on win2:win0 bits in the cancon register. 4: canstat register is repeated in these locations to simplify application firmware. unique names are given for each instance of the canstat register due to the microchip header file requirement. 5: these registers are not implemented on the pic18f248 and pic18f258. ? 2006 microchip technology inc. ds41159e-page 49 pic18fxx8 table 4-2: register file summary file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: tosu ? ? ? top-of-stack upper byte (tos<20:16>) ---0 0000 30, 38 tosh top-of-stack high byte (tos<15:8>) 0000 0000 30, 38 tosl top-of-stack low byte (tos<7:0>) 0000 0000 30, 38 stkptr stkful stkunf ? return stack pointer 00-0 0000 30, 39 pclatu ? ?bit 21 (2) holding register for pc<20:16> ---0 0000 30, 40 pclath holding register for pc<15:8> 0000 0000 30, 40 pcl pc low byte (pc<7:0>) 0000 0000 30, 40 tblptru ? ?bit 21 (2) program memory table pointer upper byte (tblptr<20:16>) --00 0000 30, 68 tblptrh program memory table pointer high byte (tblptr<15:8>) 0000 0000 30, 68 tblptrl program memory table pointer low byte (tblptr<7:0>) 0000 0000 30, 68 tablat program memory table latch 0000 0000 30, 68 prodh product register high byte xxxx xxxx 30, 75 prodl product register low byte xxxx xxxx 30, 75 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 30, 79 intcon2 rbpu intedg0 intedg1 ? ?tmr0ip ?rbip 111- -1-1 30, 80 intcon3 int2ip int1ip ?int2ieint1ie ? int2if int1if 11-0 0-00 30, 81 indf0 uses contents of fsr0 to address data memory ? value of fsr0 not changed (not a physical register) n/a 30, 55 postinc0 uses contents of fsr0 to address data memory ? value of fsr0 post-incremented (not a physical register) n/a 30, 55 postdec0 uses contents of fsr0 to address data memory ? value of fsr0 post-incremented (not a physical register) n/a 30, 55 preinc0 uses contents of fsr0 to address data memory ? value of fsr0 pre-incremented (not a physical register) n/a 30, 55 plusw0 uses contents of fsr0 to address data memory ? value of fsr0 offset by w (not a physical register) n/a 30, 55 fsr0h ? ? ? ? indirect data memory address pointer 0 high ---- xxxx 30, 55 fsr0l indirect data memory address pointer 0 low byte xxxx xxxx 30, 55 wreg working register xxxx xxxx 30, 55 indf1 uses contents of fsr1 to address data memory ? value of fsr1 not changed (not a physical register) n/a 30, 55 postinc1 uses contents of fsr1 to address data memory ? value of fsr1 post-incremented (not a physical register) n/a 30, 55 postdec1 uses contents of fsr1 to address data memory ? value of fsr1 post-incremented (not a physical register) n/a 30, 55 preinc1 uses contents of fsr1 to address data memory ? value of fsr1 pre-incremented (not a physical register) n/a 30, 55 plusw1 uses contents of fsr1 to address data memory ? value of fsr1 offset by w (not a physical register) n/a 30, 55 fsr1h ? ? ? ? indirect data memory address pointer 1 high ---- xxxx 31, 55 fsr1l indirect data memory address pointer 1 low byte xxxx xxxx 31, 55 bsr ? ? ? ? bank select register ---- 0000 31, 54 indf2 uses contents of fsr2 to address data memory ? value of fsr2 not changed (not a physical register) n/a 31, 55 postinc2 uses contents of fsr2 to address data memory ? value of fsr2 post-incremented (not a physical register) n/a 31, 55 postdec2 uses contents of fsr2 to address data memory ? value of fsr2 post-incremented (not a physical register) n/a 31, 55 preinc2 uses contents of fsr2 to address data memory ? value of fsr2 pre-incremented (not a physical register) n/a 31, 55 plusw2 uses contents of fsr2 to address data memory ? value of fsr2 offset by w (not a physical register) n/a 31, 55 fsr2h ? ? ? ? indirect data memory address pointer 2 high ---- xxxx 31, 55 fsr2l indirect data memory address pointer 2 low byte xxxx xxxx 31, 55 status ? ? ?novzdcc ---x xxxx 31, 57 tmr0h timer0 register high byte 0000 0000 31, 111 tmr0l timer0 register low byte xxxx xxxx 31, 111 t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 31, 109 osccon ? ? ? ? ? ? ?scs ---- ---0 31, 20 lvdcon ? ? irvst lvden lvdl3 lvdl2 lvdl1 lvdl0 --00 0101 31, 261 wdtcon ? ? ? ? ? ? ?swdten ---- ---0 31, 272 rcon ipen ? ?ri to pd por bor 0--1 110q 31, 58, 91 legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: these registers or register bits are not implemented on the pic18f248 and pic18f258 and read as ? 0 ?s. 2: bit 21 of the tblptru allows access to the device configuration bits. 3: ra6 and associated bits are configured as port pins in rcio and ecio oscillator mode only and read ? 0 ? in all other oscillator modes. pic18fxx8 ds41159e-page 50 ? 2006 microchip technology inc. tmr1h timer1 register high byte xxxx xxxx 31, 116 tmr1l timer1 register low byte xxxx xxxx 31, 116 t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 31, 113 tmr2 timer2 register 0000 0000 31, 118 pr2 timer2 period register 1111 1111 31, 118 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 31, 117 sspbuf ssp receive buffer/transmit register xxxx xxxx 31, 146 sspadd ssp address register in i 2 c? slave mode. ssp baud rate reload register in i 2 c master mode. 0000 0000 31, 152 sspstat smp cke d/a psr/w ua bf 0000 0000 31, 144, 153 sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 31, 145, 145 sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 31, 155 adresh a/d result register high byte xxxx xxxx 31, 243 adresl a/d result register low byte xxxx xxxx 31, 243 adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done ?adon 0000 00-0 31, 241 adcon1 adfm adcs2 ? ? pcfg3 pcfg2 pcfg1 pcfg0 00-- 0000 32, 242 ccpr1h capture/compare/pwm register 1 high byte xxxx xxxx 32, 124 ccpr1l capture/compare/pwm register 1 low byte xxxx xxxx 32, 124 ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 32, 123 eccpr1h (1) enhanced capture/compare/pwm register 1 high byte xxxx xxxx 32, 133 eccpr1l (1) enhanced capture/compare/pwm register 1 low byte xxxx xxxx 32, 133 eccp1con (1) epwm1m1 epwm1m0 edc1b1 edc1b0 eccp1m3 eccp1m2 eccp1m1 eccp1m0 0000 0000 32, 131 eccp1del (1) epdc7 epdc6 epdc5 epdc4 epdc3 epdc2 epdc1 epdc0 0000 0000 32, 140 eccpas (1) eccpase eccpas2 eccpas1 eccpas0 pssac1 pssac0 pssbd1 pssbd0 0000 0000 32, 142 cvrcon (1) cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 0000 0000 32, 255 cmcon (1) c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0000 32, 249 tmr3h timer3 register high byte xxxx xxxx 32, 121 tmr3l timer3 register low byte xxxx xxxx 32, 121 t3con rd16 t3eccp1 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 32, 119 spbrg usart baud rate generator 0000 0000 32, 185 rcreg usart receive register 0000 0000 32, 191 txreg usart transmit register 0000 0000 32, 189 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 32, 183 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 32, 184 eeadr eeprom address register xxxx xxxx 32, 59 eedata eeprom data register xxxx xxxx 32, 59 eecon2 eeprom control register 2 (not a physical register) xxxx xxxx 32, 59 eecon1 eepgd cfgs ? free wrerr wren wr rd xx-0 x000 32, 60, 67 ipr3 irxip wakip errip txb2ip txb1ip txb0ip rxb1ip rxb0ip 1111 1111 32, 90 pir3 irxif wakif errif txb2if txb1if txb0if rxb1if rxb0if 0000 0000 32, 84 pie3 irxie wakie errie txb2ie txb1ie txb0ie rxb1ie rxb0ie 0000 0000 32, 87 ipr2 ?cmip ? eeip bclip lvdip tmr3ip eccp1ip (1) -1-1 1111 32, 89 pir2 ?cmif ? eeif bclif lvdif tmr3if eccp1if (1) -0-0 0000 32, 83 pie2 ?cmie ? eeie bclie lvdie tmr3ie eccp1ie (1) -0-0 0000 32, 86 table 4-2: register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: these registers or register bits are not implemented on the pic18f248 and pic18f258 and read as ? 0 ?s. 2: bit 21 of the tblptru allows access to the device configuration bits. 3: ra6 and associated bits are configured as port pins in rcio and ecio oscillator mode only and read ? 0 ? in all other oscillator modes. ? 2006 microchip technology inc. ds41159e-page 51 pic18fxx8 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 32, 88 pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 32, 82 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 32, 85 trise (1) ibf obf ibov pspmode ? data direction bits for porte (1) 0000 -111 33, 105 trisd (1) data direction control register for portd (1) 1111 1111 33, 102 trisc data direction control register for portc 1111 1111 33, 100 trisb data direction control register for portb 1111 1111 33, 96 trisa (3) ? data direction control register for porta -111 1111 33, 93 late (1) ? ? ? ? ? read porte data latch, write porte data latch (1) ---- -xxx 33, 104 latd (1) read portd data latch, write portd data latch (1) xxxx xxxx 33, 102 latc read portc data latch, write portc data latch xxxx xxxx 33, 100 latb read portb data latch, write portb data latch xxxx xxxx 33, 96 lata (3) ? read porta data latch, write porta data latch -xxx xxxx 33, 93 porte (1) ? ? ? ? ? read porte pins, write porte data latch (1) ---- -xxx 33, 104 portd (1) read portd pins, write portd data latch (1) xxxx xxxx 33, 102 portc read portc pins, write portc data latch xxxx xxxx 33, 100 portb read portb pins, write portb data latch xxxx xxxx 33, 96 porta (3) ? read porta pins, write porta data latch -x0x 0000 33, 93 txerrcnt tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 0000 0000 33, 209 rxerrcnt rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 0000 0000 33, 214 comstat rxb0ovfl rxb1ovfl txbo txbp rxbp txwarn rxwarn ewarn 0000 0000 33, 205 ciocon ? ? endrhi cancap ? ? ? ? --00 ---- 33, 221 brgcon3 ? wakfil ? ? ? seg2ph2 seg2ph1 seg2ph0 -0-- -000 33, 220 brgcon2 seg2phts sam seg1ph2 seg1ph1 seg1ph0 prseg2 prseg1 prseg0 0000 0000 33, 219 brgcon1 sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 0000 0000 33, 218 cancon reqop2 reqop1 reqop0 abat win2 win1 win0 ? xxxx xxx- 33, 201 canstat opmode2 opmode1 opmode0 ? icode2 icode1 icode0 ? xxx- xxx- 33, 202 rxb0d7 rxb0d77 rxb0d76 rxb0d75 rxb0d74 rxb0d73 rxb0d72 rxb0d71 rxb0d70 xxxx xxxx 33, 214 rxb0d6 rxb0d67 rxb0d66 rxb0d65 rxb0d64 rxb0d63 rxb0d62 rxb0d61 rxb0d60 xxxx xxxx 33, 214 rxb0d5 rxb0d57 rxb0d56 rxb0d55 rxb0d54 rxb0d53 rxb0d52 rxb0d51 rxb0d50 xxxx xxxx 33, 214 rxb0d4 rxb0d47 rxb0d46 rxb0d45 rxb0d44 rxb0d43 rxb0d42 rxb0d41 rxb0d40 xxxx xxxx 33, 214 rxb0d3 rxb0d37 rxb0d36 rxb0d35 rxb0d34 rxb0d33 rxb0d32 rxb0d31 rxb0d30 xxxx xxxx 33, 214 rxb0d2 rxb0d27 rxb0d26 rxb0d25 rxb0d24 rxb0d23 rxb0d22 rxb0d21 rxb0d20 xxxx xxxx 33, 214 rxb0d1 rxb0d17 rxb0d16 rxb0d15 rxb0d14 rxb0d13 rxb0d12 rxb0d11 rxb0d10 xxxx xxxx 33, 214 rxb0d0 rxb0d07 rxb0d06 rxb0d05 rxb0d04 rxb0d03 rxb0d02 rxb0d01 rxb0d00 xxxx xxxx 33, 214 rxb0dlc ? rxrtr rb1 rb0 dlc3 dlc2 dlc1 dlc0 -xxx xxxx 34, 213 rxb0eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx 34, 213 rxb0eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx 34, 212 rxb0sidl sid2 sid1 sid0 srr exid ?eid17eid16 xxxx x-xx 34, 212 rxb0sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx 34, 212 rxb0con rxful rxm1 rxm0 ? rxrtrro rxb0dben jtoff filhit0 000- 0000 34, 210 table 4-2: register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: these registers or register bits are not implemented on the pic18f248 and pic18f258 and read as ? 0 ?s. 2: bit 21 of the tblptru allows access to the device configuration bits. 3: ra6 and associated bits are configured as port pins in rcio and ecio oscillator mode only and read ? 0 ? in all other oscillator modes. pic18fxx8 ds41159e-page 52 ? 2006 microchip technology inc. canstatro1 opmode2 opmode1 opmode0 ? icode2 icode1 icode0 ? xxx- xxx- 33, 202 rxb1d7 rxb1d77 rxb1d76 rxb1d75 rxb1d74 rxb1d73 rxb1d72 rxb1d71 rxb1d70 xxxx xxxx 34, 214 rxb1d6 rxb1d67 rxb1d66 rxb1d65 rxb1d64 rxb1d63 rxb1d62 rxb1d61 rxb1d60 xxxx xxxx 34, 214 rxb1d5 rxb1d57 rxb1d56 rxb1d55 rxb1d54 rxb1d53 rxb1d52 rxb1d51 rxb1d50 xxxx xxxx 34, 214 rxb1d4 rxb1d47 rxb1d46 rxb1d45 rxb1d44 rxb1d43 rxb1d42 rxb1d41 rxb1d40 xxxx xxxx 34, 214 rxb1d3 rxb1d37 rxb1d36 rxb1d35 rxb1d34 rxb1d33 rxb1d32 rxb1d31 rxb1d30 xxxx xxxx 34, 214 rxb1d2 rxb1d27 rxb1d26 rxb1d25 rxb1d24 rxb1d23 rxb1d22 rxb1d21 rxb1d20 xxxx xxxx 34, 214 rxb1d1 rxb1d17 rxb1d16 rxb1d15 rxb1d14 rxb1d13 rxb1d12 rxb1d11 rxb1d10 xxxx xxxx 34, 214 rxb1d0 rxb1d07 rxb1d06 rxb1d05 rxb1d04 rxb1d03 rxb1d02 rxb1d01 rxb1d00 xxxx xxxx 34, 214 rxb1dlc ? rxrtr rb1 rb0 dlc3 dlc2 dlc1 dlc0 -xxx xxxx 34, 213 rxb1eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx 34, 213 rxb1eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx 34, 212 rxb1sidl sid2 sid1 sid0 srr exid ?eid17eid16 xxxx x-xx 34, 212 rxb1sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx 34, 212 rxb1con rxful rxm1 rxm0 ? rxrtrro filhit2 filhit1 filhit0 000- 0000 34, 211 canstatro2 opmode2 opmode1 opmode0 ? icode2 icode1 icode0 ? xxx- xxx- 33, 202 txb0d7 txb0d77 txb0d76 txb0d75 txb0d74 txb0d73 txb0d72 txb0d71 txb0d70 xxxx xxxx 34, 208 txb0d6 txb0d67 txb0d66 txb0d65 txb0d64 txb0d63 txb0d62 txb0d61 txb0d60 xxxx xxxx 34, 208 txb0d5 txb0d57 txb0d56 txb0d55 txb0d54 txb0d53 txb0d52 txb0d51 txb0d50 xxxx xxxx 34, 208 txb0d4 txb0d47 txb0d46 txb0d45 txb0d44 txb0d43 txb0d42 txb0d41 txb0d40 xxxx xxxx 34, 208 txb0d3 txb0d37 txb0d36 txb0d35 txb0d34 txb0d33 txb0d32 txb0d31 txb0d30 xxxx xxxx 34, 208 txb0d2 txb0d27 txb0d26 txb0d25 txb0d24 txb0d23 txb0d22 txb0d21 txb0d20 xxxx xxxx 34, 208 txb0d1 txb0d17 txb0d16 txb0d15 txb0d14 txb0d13 txb0d12 txb0d11 txb0d10 xxxx xxxx 34, 208 txb0d0 txb0d07 txb0d06 txb0d05 txb0d04 txb0d03 txb0d02 txb0d01 txb0d00 xxxx xxxx 34, 208 txb0dlc ?txrtr ? ? dlc3 dlc2 dlc1 dlc0 -x-- xxxx 34, 209 txb0eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx 34, 208 txb0eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx 34, 207 txb0sidl sid2 sid1 sid0 ? exide ?eid17eid16 xxx- x-xx 34, 207 txb0sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx 35, 207 txb0con ? txabt txlarb txerr txreq ? txpri1 txpri0 -000 0-00 35, 206 canstatro3 opmode2 opmode1 opmode0 ? icode2 icode1 icode0 ? xxx- xxx- 33, 202 txb1d7 txb1d77 txb1d76 txb1d75 txb1d74 txb1d73 txb1d72 txb1d71 txb1d70 xxxx xxxx 35, 208 txb1d6 txb1d67 txb1d66 txb1d65 txb1d64 txb1d63 txb1d62 txb1d61 txb1d60 xxxx xxxx 35, 208 txb1d5 txb1d57 txb1d56 txb1d55 txb1d54 txb1d53 txb1d52 txb1d51 txb1d50 xxxx xxxx 35, 208 txb1d4 txb1d47 txb1d46 txb1d45 txb1d44 txb1d43 txb1d42 txb1d41 txb1d40 xxxx xxxx 35, 208 txb1d3 txb1d37 txb1d36 txb1d35 txb1d34 txb1d33 txb1d32 txb1d31 txb1d30 xxxx xxxx 35, 208 txb1d2 txb1d27 txb1d26 txb1d25 txb1d24 txb1d23 txb1d22 txb1d21 txb1d20 xxxx xxxx 35, 208 txb1d1 txb1d17 txb1d16 txb1d15 txb1d14 txb1d13 txb1d12 txb1d11 txb1d10 xxxx xxxx 35, 208 txb1d0 txb1d07 txb1d06 txb1d05 txb1d04 txb1d03 txb1d02 txb1d01 txb1d00 xxxx xxxx 35, 208 txb1dlc ?txrtr ? ? dlc3 dlc2 dlc1 dlc0 -x-- xxxx 35, 209 txb1eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx 35, 208 txb1eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx 35, 207 txb1sidl sid2 sid1 sid0 ? exide ?eid17eid16 xxx- x-xx 35, 207 txb1sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx 35, 207 txb1con ? txabt txlarb txerr txreq ? txpri1 txpri0 0000 0000 35, 206 table 4-2: register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: these registers or register bits are not implemented on the pic18f248 and pic18f258 and read as ? 0 ?s. 2: bit 21 of the tblptru allows access to the device configuration bits. 3: ra6 and associated bits are configured as port pins in rcio and ecio oscillator mode only and read ? 0 ? in all other oscillator modes. ? 2006 microchip technology inc. ds41159e-page 53 pic18fxx8 canstatro4 opmode2 opmode1 opmode0 ? icode2 icode1 icode0 ? xxx- xxx- 33, 202 txb2d7 txb2d77 txb2d76 txb2d75 txb2d74 txb2d73 txb2d72 txb2d71 txb2d70 xxxx xxxx 35, 208 txb2d6 txb2d67 txb2d66 txb2d65 txb2d64 txb2d63 txb2d62 txb2d61 txb2d60 xxxx xxxx 35, 208 txb2d5 txb2d57 txb2d56 txb2d55 txb2d54 txb2d53 txb2d52 txb2d51 txb2d50 xxxx xxxx 35, 208 txb2d4 txb2d47 txb2d46 txb2d45 txb2d44 txb2d43 txb2d42 txb2d41 txb2d40 xxxx xxxx 35, 208 txb2d3 txb2d37 txb2d36 txb2d35 txb2d34 txb2d33 txb2d32 txb2d31 txb2d30 xxxx xxxx 35, 208 txb2d2 txb2d27 txb2d26 txb2d25 txb2d24 txb2d23 txb2d22 txb2d21 txb2d20 xxxx xxxx 35, 208 txb2d1 txb2d17 txb2d16 txb2d15 txb2d14 txb2d13 txb2d12 txb2d11 txb2d10 xxxx xxxx 35, 208 txb2d0 txb2d07 txb2d06 txb2d05 txb2d04 txb2d03 txb2d02 txb2d01 txb2d00 xxxx xxxx 35, 208 txb2dlc ?txrtr ? ? dlc3 dlc2 dlc1 dlc0 -x-- xxxx 35, 209 txb2eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx 35, 208 txb2eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx 35, 207 txb2sidl sid2 sid1 sid0 ? exide ?eid17eid16 xxx- x-xx 35, 207 txb2sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx 35, 207 txb2con ? txabt txlarb txerr txreq ? txpri1 txpri0 -000 0-00 35, 206 rxm1eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx 35, 217 rxm1eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx 35, 217 rxm1sidl sid2 sid1 sid0 ? ? ?eid17eid16 xxx- --xx 36, 217 rxm1sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx 36, 216 rxm0eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx 36, 217 rxm0eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx 36, 217 rxm0sidl sid2 sid1 sid0 ? ? ?eid17eid16 xxx- --xx 36, 217 rxm0sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx 36, 216 rxf5eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx 36, 216 rxf5eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx 36, 216 rxf5sidl sid2 sid1 sid0 ?exiden ?eid17eid16 xxx- x-xx 36, 215 rxf5sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx 36, 215 rxf4eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx 36, 216 rxf4eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx 36, 216 rxf4sidl sid2 sid1 sid0 ?exiden ?eid17eid16 xxx- x-xx 36, 215 rxf4sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx 36, 215 rxf3eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx 36, 216 rxf3eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx 36, 216 rxf3sidl sid2 sid1 sid0 ?exiden ?eid17eid16 xxx- x-xx 36, 215 rxf3sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx 36, 215 rxf2eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx 36, 216 rxf2eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx 36, 216 rxf2sidl sid2 sid1 sid0 ?exiden ?eid17eid16 xxx- x-xx 36, 215 rxf2sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx 36, 215 rxf1eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx 36, 216 rxf1eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx 36, 216 rxf1sidl sid2 sid1 sid0 ?exiden ?eid17eid16 xxx- x-xx 36, 215 rxf1sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx 36, 215 rxf0eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx 36, 216 rxf0eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx 36, 216 rxf0sidl sid2 sid1 sid0 ?exiden ?eid17eid16 xxx- x-xx 36, 215 rxf0sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx 36, 215 table 4-2: register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: these registers or register bits are not implemented on the pic18f248 and pic18f258 and read as ? 0 ?s. 2: bit 21 of the tblptru allows access to the device configuration bits. 3: ra6 and associated bits are configured as port pins in rcio and ecio oscillator mode only and read ? 0 ? in all other oscillator modes. pic18fxx8 ds41159e-page 54 ? 2006 microchip technology inc. 4.10 access bank the access bank is an architectural enhancement that is very useful for c compiler code optimization. the techniques used by the c compiler are also useful for programs written in assembly. this data memory region can be used for: ? intermediate computational values ? local variables of subroutines ? faster context saving/switching of variables ? common variables ? faster evaluation/control of sfrs (no banking) the access bank is comprised of the upper 160 bytes in bank 15 (sfrs) and the lower 96 bytes in bank 0. these two sections will be referred to as access bank high and access bank low, respectively. figure 4-6 indicates the access bank areas. a bit in the instruction word specifies if the operation is to occur in the bank specified by the bsr register or in the access bank. when forced in the access bank (a = 0 ), the last address in access bank low is followed by the first address in access bank high. access bank high maps most of the special function registers so that these registers can be accessed without any software overhead. 4.11 bank select register (bsr) the need for a large general purpose memory space dictates a ram banking scheme. the data memory is partitioned into sixteen banks. when using direct addressing, the bsr should be configured for the desired bank. bsr<3:0> holds the upper 4 bits of the 12-bit ram address. the bsr<7:4> bits will always read ? 0 ?s and writes will have no effect. a movlb instruction has been provided in the instruction set to assist in selecting banks. if the currently selected bank is not implemented, any read will return all ? 0 ?s and all writes are ignored. the status register bits will be set/cleared as appropriate for the instruction performed. each bank extends up to ffh (256 bytes). all data memory is implemented as static ram. a movff instruction ignores the bsr since the 12-bit addresses are embedded into the instruction word. section 4.12 ?indirect addressing, indf and fsr registers? provides a description of indirect address- ing, which allows linear addressing of the entire ram space. figure 4-7: direct addressing note 1: for register file map detail, see table 4-1. 2: the access bit of the instruction can be used to force an override of the selected bank (bsr<3:0>) to the registers of the access bank. 3: the movff instruction embeds the entire 12-bit address in the instruction. data memory (1) direct addressing bank select (2) location select (3) bsr<3:0> 7 0 from opcode (3) 00h 01h 0eh 0fh bank 0 bank 1 bank 14 bank 15 1ffh 100h 0ffh 000h 0effh 0e00h 0fffh 0f00h ? 2006 microchip technology inc. ds41159e-page 55 pic18fxx8 4.12 indirect addressing, indf and fsr registers indirect addressing is a mode of addressing data mem- ory where the data memory address in the instruction is not fixed. a sfr register is used as a pointer to the data memory location that is to be read or written. since this pointer is in ram, the contents can be modified by the program. this can be useful for data tables in the data memory and for software stacks. figure 4-8 shows the operation of indirect addressing. this shows the moving of the value to the data memory address specified by the value of the fsr register. indirect addressing is possible by using one of the indf registers. any instruction using the indf register actually accesses the register indicated by the file select regis- ter, fsr. reading the indf register itself, indirectly (fsr = 0 ), will read 00h. writing to the indf register indirectly, results in a no operation. the fsr register contains a 12-bit address which is shown in figure 4-8. the indfn (0 n 2) register is not a physical register. addressing indfn actually addresses the register whose address is contained in the fsrn register (fsrn is a pointer). this is indirect addressing. example 4-5 shows a simple use of indirect addressing to clear the ram in bank 1 (locations 100h-1ffh) in a minimum number of instructions. example 4-5: how to clear ram (bank 1) using indirect addressing there are three indirect addressing registers. to address the entire data memory space (4096 bytes), these registers are 12 bits wide. to store the 12 bits of addressing information, two 8-bit registers are required. these indirect addressing registers are: 1. fsr0: composed of fsr0h:fsr0l 2. fsr1: composed of fsr1h:fsr1l 3. fsr2: composed of fsr2h:fsr2l in addition, there are registers indf0, indf1 and indf2, which are not physically implemented. reading or writing to these registers activates indirect address- ing, with the value in the corresponding fsr register being the address of the data. if an instruction writes a value to indf0, the value will be written to the address indicated by fsr0h:fsr0l. a read from indf1 reads the data from the address indicated by fsr1h:fsr1l. indfn can be used in code anywhere an operand can be used. if indf0, indf1 or indf2 are read indirectly via an fsr, all ? 0 ?s are read (zero bit is set). similarly, if indf0, indf1 or indf2 are written to indirectly, the operation will be equivalent to a nop instruction and the status bits are not affected. 4.12.1 indirect addressing operation each fsr register has an i ndf register associated with it, plus four additional register addresses. performing an operation on one of these five registers determines how the fsr will be modified during indirect addressing. ? when data access is done to one of the five indfn locations, the address selected will configure the fsrn register to: - do nothing to fsrn after an indirect access (no change) ? indfn - auto-decrement fsrn after an indirect access (post-decrement) ? postdecn - auto-increment fsrn after an indirect access (post-increment) ? postincn - auto-increment fsrn before an indirect access (pre-increment) ? preincn - use the value in the wreg register as an offset to fsrn. do not modify the value of the wreg or the fsrn register after an indirect access (no change) ? pluswn when using the auto-increment or auto-decrement features, the effect on the fsr is not reflected in the status register. for example, if the indirect address causes the fsr to equal ? 0 ?, the z bit will not be set. incrementing or decrementing an fsr affects all 12 bits. that is, when fsrnl overflows from an increment, fsrnh will be incremented automatically. adding these features allows the fsrn to be used as a software stack pointer in addition to its uses for table operations in data memory. each fsr has an address associated with it that performs an indexed indirect access. when a data access to this indfn location (pluswn) occurs, the fsrn is configured to add the 2?s complement value in the wreg register and the value in fsr to form the address before an indirect access. the fsr value is not changed. if an fsr register contains a value that indicates one of the indfn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a nop (status bits are not affected). if an indirect addressing operation is done where the target address is an fsrnh or fsrnl register, the write operation will dominate over the pre- or post-increment/decrement functions. lfsr fsr0, 100h ; next clrf postinc0 ; clear indf ; register ; & inc pointer btfss fsr0h, 1 ; all done ; w/ bank1? bra next ; no, clear next continue ; : ; yes, continue pic18fxx8 ds41159e-page 56 ? 2006 microchip technology inc. figure 4-8: indirect addressing note 1: for register file map detail, see table 4-1. data memory (1) indirect addressing fsr register 11 8 7 0 0fffh 0000h location select fsrnh fsrnl ? 2006 microchip technology inc. ds41159e-page 57 pic18fxx8 4.13 status register the status register, shown in register 4-2, contains the arithmetic status of the alu. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc, c, ov or n bits, then the write to these five bits is disabled. these bits are set or cleared according to the device logic. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf, movff and movwf instructions are used to alter the status register, because these instructions do not affect the z, c, dc, ov or n bits from the status register. for other instructions which do not affect the status bits, see table 25-2. register 4-2: status register note: the c and dc bits operate as a borrow and digit borrow bit respectively, in subtraction. u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ?novzdcc bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4 n: negative bit this bit is used for signed arithmetic (2?s complement). it indicates whether the result of the alu operation was negative (alu msb = 1 ). 1 = result was negative 0 = result was positive bit 3 ov: overflow bit this bit is used for signed arithmetic (2?s complement). it indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7) to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit for addwf, addlw, sublw and subwf instructions: 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result note: for borrow, the polarity is reversed. a subtraction is executed by adding the 2?s complement of the second operand. for rotate ( rrcf, rrncf, rlcf and rlncf ) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. bit 0 c: carry/borrow bit for addwf, addlw, sublw and subwf instructions: 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow, the polarity is reversed. a subtraction is executed by adding the 2?s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the high or low-order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 58 ? 2006 microchip technology inc. 4.14 rcon register the reset control (rcon) register contains flag bits that allow differentiation between the sources of a device reset. these flags include the to , pd , por , bor and ri bits. this register is readable and writable. register 4-3: rcon: reset control register note 1: if the boren configuration bit is set, bor is ? 1 ? on power-on reset. if the boren configuration bit is clear, bor is unknown on power-on reset. the bor status bit is a ?don?t care? and is not necessarily predictable if the brown- out circuit is disabled (the boren config- uration bit is clear). bor must then be set by the user and checked on subsequent resets to see if it is clear, indicating a brown-out has occurred. 2: it is recommended that the por bit be set after a power-on reset has been detected, so that subsequent power-on resets may be detected. r/w-0 u-0 u-0 r/w-1 r/w r/w r/w-0 r/w-0 ipen ? ?ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16cxxx compatibility mode) bit 6-5 unimplemented: read as ? 0 ? bit 4 ri : reset instruction flag bit 1 = the reset instruction was not executed 0 = the reset instruction was executed causing a device reset (must be set in software after a brown-out reset occurs) bit 3 to : watchdog time-out flag bit 1 = after power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 2 pd : power-down detection flag bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 1 por : power-on reset status bit 1 = a power-on reset has not occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = a brown-out reset has not occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 59 pic18fxx8 5.0 data eeprom memory the data eeprom is readable and writable during normal operation over the entire v dd range. the data memory is not directly mapped in the register file space. instead, it is indirectly addressed through the special function registers (sfr). there are four sfrs used to read and write the program and data eeprom memory. these registers are: ? eecon1 ? eecon2 ? eedata ? eeadr the eeprom data memory allows byte read and write. when interfacing to the data memory block, eedata holds the 8-bit data for read/write and eeadr holds the address of the eeprom location being accessed. the pic18fxx8 devices have 256 bytes of data eeprom with an address range from 00h to ffh. the eeprom data memory is rated for high erase/ write cycles. a byte write automatically erases the loca- tion and writes the new data (erase-before-write). the write time is controlled by an on-chip timer. the write time will vary with voltage and temperature, as well as from chip-to-chip. please refer to the specifications for exact limits. 5.1 eeadr register the address register can address up to a maximum of 256 bytes of data eeprom. 5.2 eecon1 and eecon2 registers eecon1 is the control register for eeprom memory accesses. eecon2 is not a physical register. reading eecon2 will read all ? 0 ?s. the eecon2 register is used exclusively in the eeprom write sequence. control bits, rd and wr , initiate read and write opera- tions, respectively. these bits cannot be cleared, only set, in software. they are cleared in hardware at the completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental or premature termination of a write operation. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a mclr reset, or a wdt time-out reset, during normal oper- ation. in these situations, the user can check the wrerr bit and rewrite the location. it is necessary to reload the data and address registers (eedata and eeadr) due to the reset condition forcing the contents of the registers to zero. note: interrupt flag bit, eeif in the pir2 register, is set when write is complete. it must be cleared in software. pic18fxx8 ds41159e-page 60 ? 2006 microchip technology inc. register 5-1: eecon1: eeprom control register 1 r/w-x r/w-x u-0 r/w-0 r/w-x r/w-0 r/s-0 r/s-0 eepgd cfgs ? free wrerr wren wr rd bit 7 bit 0 bit 7 eepgd: flash program or data eeprom memory select bit 1 = access program flash memory 0 = access data eeprom memory bit 6 cfgs: flash program/data ee or configuration select bit 1 = access configuration registers 0 = access program flash or data eeprom memory bit 5 unimplemented: read as ? 0 ? bit 4 free: flash row erase enable bit 1 = erase the program memory row addressed by tblptr on the next wr command (reset by hardware) 0 = perform write only bit 3 wrerr: write error flag bit 1 = a write operation is prematurely terminated (any mclr or any wdt reset during self-timed programming in normal operation) 0 = the write operation completed note: when a wrerr occurs, the eepgd or free bits are not cleared. this allows tracing of the error condition. bit 2 wren: write enable bit 1 = allows write cycles 0 = inhibits write to the eeprom or flash memory bit 1 wr : write control bit 1 = initiates a data eeprom erase/write cycle or a program memory erase cycle or write cycle (the operation is self-timed and the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software.) 0 = write cycle is complete bit 0 rd : read control bit 1 = initiates an eeprom read (read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software. rd bit cannot be set when eepgd = 1 .) 0 = does not initiate an eeprom read legend: r = readable bit w = writable bit s = settable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 61 pic18fxx8 5.3 reading the data eeprom memory to read a data memory location, the user must write the address to the eeadr register, clear the eepgd and cfgs control bits (eecon1<7:6>) and then set control bit rd (eecon1<0>). the data is available in the very next instruction cycle of the eedata register; therefore, it can be read by the next instruction. eedata will hold this value until another read operation or until it is written to by the user (during a write operation). example 5-1: data eeprom read 5.4 writing to the data eeprom memory to write an eeprom data location, the address must first be written to the eeadr register and the data writ- ten to the eedata register. then, the sequence in example 5-2 must be followed to initiate the write cycle. the write will not initiate if the above sequence is not exactly followed (write 55h to eecon2, write 0aah to eecon2, then set wr bit) for each byte. it is strongly recommended that interrupts be disabled during this code segment. additionally, the wren bit in eecon1 must be set to enable writes. this mechanism prevents accidental writes to data eeprom due to unexpected code exe- cution (i.e., runaway programs). the wren bit should be kept clear at all times, except when updating the eeprom. the wren bit is not cleared by hardware. after a write sequence has been initiated, clearing the wren bit will not affect the current write cycle. the wr bit will be inhibited from being set unless the wren bit is set. the wren bit must be set on a previous instruc- tion. both wr and wren cannot be set with the same instruction. at the completion of the write cycle, the wr bit is cleared in hardware and the eeprom write complete interrupt flag bit (eeif) is set. the user may either enable this interrupt or roll this bit. eeif must be cleared by software. example 5-2: data eeprom write movlw data_ee_addr ; movwf eeadr ;data memory address ;to read bcf eecon1, eepgd ;point to data memory bcs eecon1, cfgs ; bsf eecon1, rd ;eeprom read movf eedata, w ;w = eedata movlw data_ee_addr ; movwf eeadr ; data memory address to read movlw data_ee_data ; movwf eedata ; data memory value to write bcf eecon1, eepgd ; point to data memory bcf eecon1, cfgs ; access program flash or data eeprom memory bsf eecon1, wren ; enable writes bcf intcon, gie ; disable interrupts required movlw 55h ; sequence movwf eecon2 ; write 55h movlw 0aah ; movwf eecon2 ; write aah bsf eecon1, wr ; set wr bit to begin write bsf intcon, gie ; enable interrupts . ; user code execution . . bcf eecon1, wren ; disable writes on write complete (eeif set) pic18fxx8 ds41159e-page 62 ? 2006 microchip technology inc. 5.5 write verify depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. generally, a write failure will be a bit which was written as a ? 1 ?, but reads back as a ? 0 ? (due to leakage off the cell). 5.6 protection against spurious write there are conditions when the device may not want to write to the data eeprom memory. to protect against spurious eeprom writes, various mechanisms have been built-in. on power-up, the wren bit is cleared. also, the power-up timer (72 ms duration) prevents eeprom write. the write initiate sequence and the wren bit together reduce the probability of an accidental write during brown-out, power glitch or software malfunction. 5.7 operation during code-protect data eeprom memory has its own code-protect mechanism. external read and write operations are disabled if either of these mechanisms are enabled. the microcontroller itself can both read and write to the internal data eeprom, regardless of the state of the code-protect configuration bit. refer to section 24.0 ?special features of the cpu? for additional information. 5.8 using the data eeprom the data eeprom is a high-endurance, byte address- able array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). frequently changing values will typically be updated more often than specification d124 or d124a. if this is not the case, an array refresh must be performed. for this reason, variables that change infrequently (such as constants, ids, calibration, etc.) should be stored in flash program memory. a simple data eeprom refresh routine is shown in example 5-3. example 5-3: data eeprom refresh routine note: if data eeprom is only used to store constants and/or data that changes rarely, an array refresh is likely not required. see specification d124 or d124a. clrf eeadr ; start at address 0 bcf eecon1, cfgs ; set for memory bcf eecon1, eepgd ; set for data eeprom bcf intcon, gie ; disable interrupts bsf eecon1, wren ; enable writes loop ; loop to refresh array bsf eecon1, rd ; read current address movlw 55h ; movwf eecon2 ; write 55h movlw 0aah ; movwf eecon2 ; write aah bsf eecon1, wr ; set wr bit to begin write btfsc eecon1, wr ; wait for write to complete bra $-2 incfsz eeadr, f ; increment address bra loop ; not zero, do it again bcf eecon1, wren ; disable writes bsf intcon, gie ; enable interrupts ? 2006 microchip technology inc. ds41159e-page 63 pic18fxx8 table 5-1: registers associated with data eeprom memory name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u eeadr eeprom address register xxxx xxxx uuuu uuuu eedata eeprom data register xxxx xxxx uuuu uuuu eecon2 eeprom control register 2 (not a physical register) ? ? eecon1 eepgd cfgs ? free wrerr wren wr rd xx-0 x000 uu-0 u000 ipr2 ?cmip ?eeipbcliplvdiptmr3ip eccp1ip (1) -1-1 1111 -1-1 1111 pir2 ? cmif ?eeifbclif lvdif tmr3if eccp1if (1) -0-0 0000 -0-0 0000 pie2 ? cmie ?eeiebclie lvdie tmr3ie eccp1ie (1) -0-0 0000 -0-0 0000 legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ? 0 ?. shaded cells are not used during flash/eeprom access. note 1: these registers or register bits are not im plemented on the pic18f248 and pic18f258 and read as ? 0 ?s. pic18fxx8 ds41159e-page 64 ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. ds41159e-page 65 pic18fxx8 6.0 flash program memory the flash program memory is readable, writable and erasable during normal operation over the entire v dd range. a read from program memory is executed on one byte at a time. a write to program memory is executed on blocks of 8 bytes at a time. program memory is erased in blocks of 64 bytes at a time. a bulk erase operation may not be issued from user code. writing or erasing program memory will cease instruc- tion fetches until the operation is complete. the program memory cannot be accessed during the write or erase, therefore, code cannot execute. an internal programming timer terminates program memory writes and erases. a value written to program memory does not need to be a valid instruction. executing a program memory location that forms an invalid instruction results in a nop . 6.1 table reads and table writes in order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data ram: ? table read ( tblrd ) ? table write ( tblwt ) the program memory space is 16 bits wide, while the data ram space is 8 bits wide. table reads and table writes move data between these two memory spaces through an 8-bit register (tablat). table read operations retrieve data from program memory and place it into the data ram space. figure 6-1 shows the operation of a table read with program memory and data ram. table write operations store data from the data memory space into holding registers in program memory. the procedure to write the contents of the holding registers into program memory is detailed in section 6.5 ?writing to flash program memory? . figure 6-2 shows the operation of a table write with program memory and data ram. table operations work with byte entities. a table block containing data, rather than program instructions, is not required to be word aligned. therefore, a table block can start and end at any byte address. if a table write is being used to write executable code into program memory, program instructions will need to be word aligned. figure 6-1: table read operation table pointer (1) table latch (8-bit) program memory tblptrh tblptrl tablat tblptru instruction: tblrd * note 1: table pointer points to a byte in program memory. program memory (tblptr) pic18fxx8 ds41159e-page 66 ? 2006 microchip technology inc. figure 6-2: table write operation 6.2 control registers several control registers are used in conjunction with the tblrd and tblwt instructions. these include the: ? eecon1 register ? eecon2 register ? tablat register ? tblptr registers 6.2.1 eecon1 and eecon2 registers eecon1 is the control register for memory accesses. eecon2 is not a physical register. reading eecon2 will read all ? 0 ?s. the eecon2 register is used exclusively in the memory write and erase sequences. control bit eepgd determines if the access will be a program or data eeprom memory access. when clear, any subsequent operations will operate on the data eeprom memory. when set, any subsequent operations will operate on the program memory. control bit cfgs determines if the access will be to the configuration/calibration registers or to program memory/data eeprom memory. when set, subsequent operations will operate on configuration registers regardless of eepgd (see section 24.0 ?special features of the cpu? ). when clear, memory selection access is determined by eepgd. the free bit, when set, will allow a program memory erase operation. when the free bit is set, the erase operation is initiated on the next wr command. when free is clear, only writes are enabled. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a mclr reset or a wdt time-out reset during normal opera- tion. in these situations, the user can check the wrerr bit and rewrite the location. it is necessary to reload the data and address registers (eedata and eeadr) due to reset values of zero. control bits, rd and wr , initiate read and write opera- tions, respectively. these bits cannot be cleared, only set, in software. they are cleared in hardware at the completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental or premature termination of a write operation. the rd bit cannot be set when accessing program memory (eepgd = 1 ). table pointer (1) table latch (8-bit) tblptrh tblptrl tablat program memory (tblptr) tblptru instruction: tblwt * note 1: table pointer actually points to one of eight holding registers, the address of which is determined by tblptrl<2:0>. the process for physically writing data to the program memory array is discussed in section 6.5 ?writing to flash program memory? . holding registers program memory note: interrupt flag bit, eeif in the pir2 register, is set when write is complete. it must be cleared in software. ? 2006 microchip technology inc. ds41159e-page 67 pic18fxx8 register 6-1: eecon1: eeprom control register 1 r/w-x r/w-x u-0 r/w-0 r/w-x r/w-0 r/s-0 r/s-0 eepgd cfgs ? free wrerr wren wr rd bit 7 bit 0 bit 7 eepgd: flash program or data eeprom memory select bit 1 = access program flash memory 0 = access data eeprom memory bit 6 cfgs: flash program/data ee or configuration select bit 1 = access configuration registers 0 = access program flash or data eeprom memory bit 5 unimplemented: read as ? 0 ? bit 4 free: flash row erase enable bit 1 = erase the program memory row addressed by tblptr on the next wr command (cleared by completion of erase operation) 0 = perform write only bit 3 wrerr: write error flag bit 1 = a write operation is prematurely terminated (any mclr or any wdt reset during self-timed programming in normal operation) 0 = the write operation completed note: when a wrerr occurs, the eepgd and cfgs bits are not cleared. this allows tracing of the error condition. bit 2 wren: write enable bit 1 = allows write cycles 0 = inhibits write to the eeprom or flash memory bit 1 wr : write control bit 1 = initiates a data eeprom erase/write cycle or a program memory erase cycle or write cycle (the operation is self-timed and the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software.) 0 = write cycle to the eeprom is complete bit 0 rd : read control bit 1 = initiates an eeprom read (read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software. rd bit cannot be set when eepgd = 1 .) 0 = does not initiate an eeprom read legend: r = readable bit w = writable bit s = settable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 68 ? 2006 microchip technology inc. 6.2.2 tablat ? table latch register the table latch (tablat) is an 8-bit register mapped into the sfr space. the table latch is used to hold 8-bit data during data transfers between program memory and data ram. 6.2.3 tblptr ? table pointer register the table pointer (tblptr) addresses a byte within the program memory. the tblptr is comprised of three sfr registers: table pointer upper byte, table pointer high byte and table pointer low byte (tblptru:tblptrh:tblptrl). these three regis- ters join to form a 22-bit wide pointer. the low-order 21 bits allow the device to address up to 2 mbytes of program memory space. the 22nd bit allows access to the device id, the user id and the configuration bits. the table pointer, tblptr, is used by the tblrd and tblwt instructions. these instructions can update the tblptr in one of four ways based on the table operation. these operations are shown in table 6-1. these operations on the tblptr only affect the low-order 21 bits. 6.2.4 table pointer boundaries tblptr is used in reads, writes and erases of the flash program memory. when a tblrd is executed, all 22 bits of the table pointer determine which byte is read from program memory into tablat. when a tblwt is executed, the three lsbs of the table pointer (tblptr<2:0>) determine which of the eight program memory holding registers is written to. when the timed write to program memory (long write) begins, the 19 msbs of the table pointer, tblptr (tblptr<21:3>), will determine which program memory block of 8 bytes is written to. for more detail, see section 6.5 ?writing to flash program memory? . when an erase of program memory is executed, the 16 msbs of the table pointer (tblptr<21:6>) point to the 64-byte block that will be erased. the least significant bits (tblptr<5:0>) are ignored. figure 6-3 describes the relevant boundaries of tblptr based on flash program memory operations. table 6-1: table pointer operations with tblrd and tblwt instructions figure 6-3: table pointer boundaries based on operation example operation on table pointer tblrd* tblwt* tblptr is not modified tblrd*+ tblwt*+ tblptr is incremented after the read/write tblrd*- tblwt*- tblptr is decremented after the read/write tblrd+* tblwt+* tblptr is incremented before the read/write 21 16 15 87 0 erase ? tblptr<21:6> write ? tblptr<21:3> read ? tblptr<21:0> tblptrl tblptrh tblptru ? 2006 microchip technology inc. ds41159e-page 69 pic18fxx8 6.3 reading the flash program memory the tblrd instruction is used to retrieve data from program memory and places it into data ram. table reads from program memory are performed one byte at a time. tblptr points to a byte address in program space. executing tblrd places the byte pointed to into tablat. in addition, tblptr can be modified automatically for the next table read operation. the internal program memory is typically organized by words. the least significant bit of the address selects between the high and low bytes of the word. figure 6-4 shows the interface between the internal program memory and the tablat. figure 6-4: reads from flash program memory example 6-1: reading a flash program memory word (even byte address) program memory (odd byte address) tblrd tablat tblptr = xxxxx1 fetch instruction register (ir) read register tblptr = xxxxx0 movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the word movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl read_word tblrd*+ ; read into tablat and increment movf tablat, w ; get data movwf word_lsb tblrd*+ ; read into tablat and increment movf tablat, w ; get data movwf word_msb pic18fxx8 ds41159e-page 70 ? 2006 microchip technology inc. 6.4 erasing flash program memory the minimum erase block is 32 words or 64 bytes. only through the use of an external programmer, or through icsp control, can larger blocks of program memory be bulk erased. word erase in the flash array is not supported. when initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased. the most significant 16 bits of the tblptr<21:6> point to the block being erased. tblptr<5:0> are ignored. the eecon1 register commands the erase operation. the eepgd bit must be set to point to the flash program memory. the wren bit must be set to enable write operations. the free bit is set to select an erase operation. for protection, the write initiate sequence for eecon2 must be used. a long write is necessary for erasing the internal flash. instruction execution is halted while in a long write cycle. the long write will be terminated by the internal programming timer. 6.4.1 flash program memory erase sequence the sequence of events for erasing a block of internal program memory location is: 1. load table pointer with address of row being erased. 2. set the eecon1 register for the erase operation: ? set the eepgd bit to point to program memory; ? clear the cfgs bit to access program memory; ? set the wren bit to enable writes; ? set the free bit to enable the erase. 3. disable interrupts. 4. write 55h to eecon2. 5. write 0aah to eecon2. 6. set the wr bit. this will begin the row erase cycle. 7. the cpu will stall for duration of the erase (about 2 ms using internal timer). 8. re-enable interrupts. example 6-2: erasing a flash program memory row movlw upper (code_addr) ; load tblptr with the base movwf tblptru ; address of the memory block movlw high (code_addr) movwf tblptrh movlw low (code_addr) movwf tblptrl erase_row bsf eecon1, eepgd ; point to flash program memory bcf eecon1, cfgs ; access flash program memory bsf eecon1, wren ; enable write to memory bsf eecon1, free ; enable row erase operation bcf intcon, gie ; disable interrupts movlw 55h movwf eecon2 ; write 55h required movlw 0aah sequence movwf eecon2 ; write 0aah bsf eecon1, wr ; start erase (cpu stall) nop ; nop needed for proper code execution bsf intcon, gie ; re-enable interrupts ? 2006 microchip technology inc. ds41159e-page 71 pic18fxx8 6.5 writing to flash program memory the minimum programming block is 4 words or 8 bytes. word or byte programming is not supported. table writes are used internally to load the holding registers needed to program the flash memory. there are 8 holding registers used by the table writes for programming. since the table latch (tablat) is only a single byte, the tblwt instruction has to be executed 8 times for each programming operation. all of the table write operations will essentially be short writes, because only the holding registers are written. at the end of updating 8 registers, the eecon1 register must be written to, to start the programming operation with a long write. the long write is necessary for programming the inter- nal flash. instruction execution is halted while in a long write cycle. the long write will be terminated by the internal programming timer. the eeprom on-chip timer controls the write time. the write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. 6.5.1 flash program memory write sequence the sequence of events for programming an internal program memory location should be: 1. read 64 bytes into ram. 2. update data values in ram as necessary. 3. load table pointer with address being erased. 4. do the row erase procedure. 5. load table pointer with address of first byte being written. 6. write the first 8 bytes into the holding registers using the tblwt instruction, auto-increment may be used. 7. set the eecon1 register for the write operation: ? set the eepgd bit to point to program memory; ? clear the cfgs bit to access program memory; ? set the wren to enable byte writes. 8. disable interrupts. 9. write 55h to eecon2. 10. write aah to eecon2. 11. set the wr bit. this will begin the write cycle. 12. the cpu will stall for duration of the write (about 2 ms using internal timer). 13. re-enable interrupts. 14. repeat steps 6-14 seven times to write 64 bytes. 15. verify the memory (table read). this procedure will require about 18 ms to update one row of 64 bytes of memory. an example of the required code is given in example 6-3. figure 6-5: table writes to flash program memory note: before setting the wr bit, the table pointer address needs to be within the intended address range of the 8 bytes in the holding registers. holding register tablat holding register tblptr = xxxxx7 holding register tblptr = xxxxx1 holding register tblptr = xxxxx0 8 8 8 8 write register tblptr = xxxxx2 program memory pic18fxx8 ds41159e-page 72 ? 2006 microchip technology inc. example 6-3: writing to flash program memory movlw d'64 ; number of bytes in erase block movwf counter movlw high (buffer_addr) ; point to buffer movwf fsr0h movlw low (buffer_addr) movwf fsr0l movlw upper (code_addr) ; load tblptr with the base movwf tblptru ; address of the memory block movlw high (code_addr) movwf tblptrh movlw low (code_addr) movwf tblptrl read_block tblrd*+ ; read into tablat, and inc movf tablat, w ; get data movwf postinc0 ; store data decfsz counter ; done? bra read_block ; repeat modify_word movlw data_addr_high ; point to buffer movwf fsr0h movlw data_addr_low movwf fsr0l movlw new_data_low ; update buffer word movwf postinc0 movlw new_data_high movwf indf0 erase_block movlw upper (code_addr) ; load tblptr with the base movwf tblptru ; address of the memory block movlw high (code_addr) movwf tblptrh movlw low (code_addr) movwf tblptrl bsf eecon1, eepgd ; point to flash program memory bcf eecon1, cfgs ; access flash program memory bsf eecon1, wren ; enable write to memory bsf eecon1, free ; enable row erase operation bcf intcon, gie ; disable interrupts movlw 55h required movwf eecon2 ; write 55h sequence movlw 0aah movwf eecon2 ; write aah bsf eecon1, wr ; start erase (cpu stall) nop bsf intcon, gie ; re-enable interrupts tblrd*- ; dummy read decrement write_buffer_back movlw 8 ; number of write buffer groups of 8 bytes movwf counter_hi movlw high (buffer_addr) ; point to buffer movwf fsr0h movlw low (buffer_addr) movwf fsr0l program_loop movlw 8 ; number of bytes in holding register movwf counter write_word_to_hregs movfw postinc0, w ; get low byte of buffer data movwf tablat ; present data to table latch tblwt+* ; write data, perform a short write ; to internal tblwt holding register. decfsz counter ; loop until buffers are full bra write_word_to_hregs ? 2006 microchip technology inc. ds41159e-page 73 pic18fxx8 example 6-3: writing to flash program memory (continued) 6.5.2 write verify depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. 6.5.3 unexpected termination of write operation if a write is terminated by an unplanned event, such as loss of power or an unexpected reset, the memory location just programmed should be verified and repro- grammed if needed.the wrerr bit is set when a write operation is interrupted by a mclr reset or a wdt time-out reset during normal operation. in these situations, users can check the wrerr bit and rewrite the location. 6.5.4 protection against spurious writes to reduce the probability against spurious writes to flash program memory, the write initiate sequence must also be followed. see section 24.0 ?special features of the cpu? for more detail. 6.6 flash program operation during code protection see section 24.0 ?special features of the cpu? for details on code protection of flash program memory. write_word_to_hregs movfw postinc0, w ; get low byte of buffer data movwf tablat ; present data to table latch tblwt+* ; write data, perform a short write ; to internal tblwt holding register. decfsz counter ; loop until buffers are full bra write_word_to_hregs program_memory bsf eecon1, eepgd ; point to flash program memory bcf eecon1, cfgs ; access flash program memory bsf eecon1, wren ; enable write to memory bcf intcon, gie ; disable interrupts movlw 55h ; write 55h required movwf eecon2 sequence movlw 0aah ; write 0aah movwf eecon2 ; start program (cpu stall) bsf eecon1, wr nop bsf intcon, gie ; re-enable interrupts decfsz counter_hi ; loop until done bra program_loop bcf eecon1, wren ; disable write to memory pic18fxx8 ds41159e-page 74 ? 2006 microchip technology inc. table 6-2: registers associated with program flash memory name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets tblptru ? ? bit 21 program memory table pointer upper byte (tblptr<20:16>) --00 0000 --00 0000 tbpltrh program memory table pointer high byte (tblptr<15:8>) 0000 0000 0000 0000 tblptrl program memory table pointer low byte (tblptr<7:0>) 0000 0000 0000 0000 tablat program memory table latch 0000 0000 0000 0000 intcon gie/gieh peie/ giel tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u eecon2 eeprom control register 2 (not a physical register) ? ? eecon1 eepgd cfgs ? free wrerr wren wr rd xx-0 x000 uu-0 u000 ipr2 ?cmip ?eeipbcliplvdiptmr3ip eccp1ip (1) -1-1 1111 -1-1 1111 pir2 ?cmif ? eeif bclif lvdif tmr3if eccp1if (1) -0-0 0000 -0-0 0000 pie2 ?cmie ?eeiebclielvdietmr3ie eccp1ie (1) -0-0 0000 -0-0 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used during flash/eeprom access. note 1: these registers or register bi ts are not implemented on the pic18f248 and pic18f258 and read as ? 0 ?s. ? 2006 microchip technology inc. ds41159e-page 75 pic18fxx8 7.0 8 x 8 hardware multiplier 7.1 introduction an 8 x 8 hardware multiplier is included in the alu of the pic18fxx8 devices. by making the multiply a hardware operation, it completes in a single instruction cycle. this is an unsigned multiply that gives a 16-bit result. the result is stored in the 16-bit product register pair (prodh:prodl). the multiplier does not affect any flags in the alusta register. making the 8 x 8 multiplier execute in a single cycle gives the following advantages: ? higher computational throughput ? reduces code size requirements for multiply algorithms the performance increase allows the device to be used in applications previously reserved for digital signal processors. table 7-1 shows a performance comparison between enhanced devices using the single-cycle hardware multiply and performing the same function without the hardware multiply. 7.2 operation example 7-1 shows the sequence to do an 8 x 8 unsigned multiply. only one instruction is required when one argument of the multiply is already loaded in the wreg register. example 7-2 shows the sequence to do an 8 x 8 signed multiply. to account for the sign bits of the arguments, each argument?s most significant bit (msb) is tested and the appropriate subtractions are done. example 7-1: 8 x 8 unsigned multiply routine example 7-2: 8 x 8 signed multiply routine table 7-1: performance comparison movf arg1, w ; mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl movf arg1, w mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl btfsc arg2, sb ; test sign bit subwf prodh ; prodh = prodh ; - arg1 movf arg2, w btfsc arg1, sb ; test sign bit subwf prodh ; prodh = prodh ; - arg2 routine multiply method program memory (words) cycles (max) time @ 40 mhz @ 10 mhz @ 4 mhz 8 x 8 unsigned without hardware multiply 13 69 6.9 s 27.6 s 69 s hardware multiply 1 1 100 ns 400 ns 1 s 8 x 8 signed without hardware multiply 33 91 9.1 s 36.4 s 91 s hardware multiply 6 6 600 ns 2.4 s6 s 16 x 16 unsigned without hardware multiply 21 242 24.2 s 96.8 s 242 s hardware multiply 24 24 2.4 s9.6 s 24 s 16 x 16 signed without hardware multiply 52 254 25.4 s102.6 s 254 s hardware multiply 36 36 3.6 s 14.4 s 36 s pic18fxx8 ds41159e-page 76 ? 2006 microchip technology inc. example 7-3 shows the sequence to do a 16 x 16 unsigned multiply. equation 7-1 shows the algorithm that is used. the 32-bit result is stored in four registers, res3:res0. equation 7-1: 16 x 16 unsigned multiplication algorithm example 7-3: 16 x 16 unsigned multiply routine example 7-4 shows the sequence to do a 16 x 16 signed multiply. equation 7-2 shows the algorithm used. the 32-bit result is stored in four registers, res3:res0. to account for the sign bits of the argu- ments, each argument pair?s most significant bit (msb) is tested and the appropriate subtractions are done. equation 7-2: 16 x 16 signed multiplication algorithm example 7-4: 16 x 16 signed multiply routine movf arg1l, w mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l, w mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1 ; add cross movf prodh, w ; products addwfc res2 ; clrf wreg ; addwfc res3 ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1 ; add cross movf prodh, w ; products addwfc res2 ; clrf wreg ; addwfc res3 ; res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) movf arg1l, w mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l, w mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1 ; add cross movf prodh, w ; products addwfc res2 ; clrf wreg ; addwfc res3 ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1 ; add cross movf prodh, w ; products addwfc res2 ; clrf wreg ; addwfc res3 ; ; btfss arg2h, 7 ; arg2h:arg2l neg? bra sign_arg1 ; no, check arg1 movf arg1l, w ; subwf res2 ; movf arg1h, w ; subwfb res3 ; sign_arg1 btfss arg1h, 7 ; arg1h:arg1l neg? bra cont_code ; no, done movf arg2l, w ; subwf res2 ; movf arg2h, w ; subwfb res3 ; cont_code : res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l)+ (-1 ? arg2h<7> ? arg1h:arg1l ? 2 16 ) + (-1 ? arg1h<7> ? arg2h:arg2l ? 2 16 ) ? 2006 microchip technology inc. ds41159e-page 77 pic18fxx8 8.0 interrupts the pic18fxx8 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. the high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. high priority interrupt events will override any low priority interrupts that may be in progress. there are 13 registers that are used to control interrupt operation. these registers are: ? rcon ?intcon ? intcon2 ? intcon3 ? pir1, pir2, pir3 ? pie1, pie2, pie3 ? ipr1, ipr2, ipr3 it is recommended that the microchip header files, supplied with mplab ? ide, be used for the symbolic bit names in these registers. this allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. each interrupt source has three bits to control its operation. the functions of these bits are: ? flag bit to indicate that an interrupt event occurred ? enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set ? priority bit to select high priority or low priority the interrupt priority feature is enabled by setting the ipen bit (rcon register). when interrupt priority is enabled, there are two bits that enable interrupts globally. setting the gieh bit (intcon<7>) enables all interrupts. setting the giel bit (intcon register) enables all interrupts that have the priority bit cleared. when the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vec- tor immediately to address 000008h or 000018h, depending on the priority level. individual interrupts can be disabled through their corresponding enable bits. when the ipen bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with picmicro ? mid-range devices. in compatibility mode, the interrupt priority bits for each source have no effect. the peie bit (intcon register) enables/disables all peripheral interrupt sources. the gie bit (intcon register) enables/disables all interrupt sources. all interrupts branch to address 000008h in compatibility mode. when an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. if the ipen bit is cleared, this is the gie bit. if interrupt priority levels are used, this will be either the gieh or giel bit. high priority interrupt sources can interrupt a low priority interrupt. the return address is pushed onto the stack and the pc is loaded with the interrupt vector address (000008h or 000018h). once in the interrupt service routine, the source(s) of the interrupt can be deter- mined by polling the interrupt flag bits. the interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. the ?return from interrupt? instruction, retfie , exits the interrupt routine and sets the gie bit (gieh or giel if priority levels are used), which re-enables interrupts. for external interrupt events, such as the int pins or the portb input change interrupt, the interrupt latency will be three to four instruction cycles. the exact latency is the same for one or two-cycle instructions. individual interrupt flag bits are set regardless of the status of their corresponding enable bit or the gie bit. note: do not use the movff instruction to modify any of the interrupt control registers while any interrupt is enabled. doing so may cause erratic microcontroller behavior. pic18fxx8 ds41159e-page 78 ? 2006 microchip technology inc. figure 8-1: interrupt logic tmr0ie gie/gieh giel/peie wake-up if in sleep mode interrupt to cpu vector to location 0008h int1if int1ie int1ip tmr0if tmr0ie tmr0ip int0if int0ie rbif rbie rbip tmr0if tmr0ip int1if int1ie int1ip rbif rbie rbip int0if int0ie peie/giel interrupt to cpu vector to location ipen 0018h peripheral interrupt flag bit peripheral interrupt enable bit peripheral interrupt priority bit peripheral interrupt flag bit peripheral interrupt enable bit peripheral interrupt priority bit tmr1if tmr1ie tmr1ip xxxxif xxxxie xxxxip additional peripheral interrupts tmr1if tmr1ie tmr1ip high priority interrupt generation low priority interrupt generation xxxxif xxxxie xxxxip additional peripheral interrupts ipen ipen gie/gieh int2if int2ie int2ip int2if int2ie int2ip ? 2006 microchip technology inc. ds41159e-page 79 pic18fxx8 8.1 intcon registers the intcon registers are readable and writable regis- ters which contain various enable, priority and flag bits. because of the number of interrupts to be controlled, pic18fxx8 devices have three intcon registers. they are detailed in register 8-1 through register 8-3. register 8-1: intcon: interrupt control register note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows software polling. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif bit 7 bit 0 bit 7 gie/gieh: global interrupt enable bit w hen ipen (rcon<7>) = 0 : 1 = enables all unmasked interrupts 0 = disables all interrupts when i p en (rcon<7>) = 1 : 1 = enables all high priority interrupts 0 = disables all priority interrupts bit 6 peie/giel: peripheral interrupt enable bit when ipen (rcon<7>) = 0 : 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts when ipen (rcon<7>) = 1 : 1 = enables all low priority peripheral interrupts 0 = disables all low priority peripheral interrupts bit 5 tmr0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 overflow interrupt 0 = disables the tmr0 overflow interrupt bit 4 int0ie: int0 external interrupt enable bit 1 = enables the int0 external interrupt 0 = disables the int0 external interrupt bit 3 rbie: rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 int0if: int0 external interrupt flag bit 1 = the int0 external interrupt occurred (must be cleared in software by reading portb) 0 = the int0 external interrupt did not occur bit 0 rbif: rb port change interrupt flag bit 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state note: a mismatch condition will continue to set this bit. reading portb will end the mismatch condition and allow the bit to be cleared. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 80 ? 2006 microchip technology inc. register 8-2: intcon2: interrupt control regi ster 2 r/w-1 r/w-1 r/w-1 u-0 u-0 r/w-1 u-0 r/w-1 rbpu intedg0 intedg1 ? ?tmr0ip ?rbip bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = all portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg0 : external interrupt 0 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 5 intedg1 : external interrupt 1 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 4-3 unimplemented: read as ? 0 ? bit 2 tmr0ip : tmr0 overflow interrupt priority bit 1 = high priority 0 = low priority bit 1 unimplemented: read as ? 0 ? bit 0 rbip : rb port change interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows software polling. ? 2006 microchip technology inc. ds41159e-page 81 pic18fxx8 register 8-3: intcon3: interrupt control register 3 r/w-1 r/w-1 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 int2ip int1ip ?int2ieint1ie ? int2if int1if bit 7 bit 0 bit 7 int2ip: int2 external interrupt priority bit 1 = high priority 0 = low priority bit 6 int1ip: int1 external interrupt priority bit 1 = high priority 0 = low priority bit 5 unimplemented: read as ? 0 ? bit 4 int2ie: int2 external interrupt enable bit 1 = enables the int2 external interrupt 0 = disables the int2 external interrupt bit 3 int1ie: int1 external interrupt enable bit 1 = enables the int1 external interrupt 0 = disables the int1 external interrupt bit 2 unimplemented: read as ? 0 ? bit 1 int2if: int2 external interrupt flag bit 1 = the int2 external interrupt occurred (must be cleared in software) 0 = the int2 external interrupt did not occur bit 0 int1if: int1 external interrupt flag bit 1 = the int1 external interrupt occurred (must be cleared in software) 0 = the int1 external interrupt did not occur legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows software polling. pic18fxx8 ds41159e-page 82 ? 2006 microchip technology inc. 8.2 pir registers the peripheral interrupt request (pir) registers contain the individual flag bits for the peripheral interrupts (register 8-4 through register 8-6). due to the number of peripheral interrupt sources, there are three peripheral interrupt request (flag) registers (pir1, pir2, pir3). register 8-4: pir1: peripheral interrupt request (flag) register 1 note 1: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit, gie (intcon register). 2: user software should ensure the appropri- ate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if bit 7 bit 0 bit 7 pspif: parallel slave port read/write interrupt flag bit (1) 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred bit 6 adif : a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5 rcif : usart receive interrupt flag bit 1 = the usart receive buffer, rcreg, is full (cleared when rcreg is read) 0 = the usart receive buffer is empty bit 4 txif : usart transmit interrupt flag bit 1 = the usart transmit buffer, txreg, is empty (cleared when txreg is written) 0 = the usart transmit buffer is full bit 3 sspif : master synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2 ccp1if : ccp1 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode. bit 1 tmr2if: tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if: tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow note 1: this bit is only available on pic18f4x8 devices. for pic18f2x8 devices, this bit is unimplemented and reads as ? 0 ?. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 83 pic18fxx8 register 8-5: pir2: peripheral interrupt request (flag) register 2 u-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?cmif (1) ? eeif bclif lvdif tmr3if eccp1if (1) bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 cmif: comparator interrupt flag bit (1) 1 = comparator input has changed 0 = comparator input has not changed bit 5 unimplemented: read as ? 0 ? bit 4 eeif: eeprom write operation interrupt flag bit 1 = write operation is complete (must be cleared in software) 0 = write operation is not complete bit 3 bclif: bus collision interrupt flag bit 1 = a bus collision occurred (must be cleared in software) 0 = no bus collision occurred bit 2 lvdif: low-voltage detect interrupt flag bit 1 = a low-voltage condition occurred (must be cleared in software) 0 = the device voltage is above the low-voltage detect trip point bit 1 tmr3if: tmr3 overflow interrupt flag bit 1 = tmr3 register overflowed (must be cleared in software) 0 = tmr3 register did not overflow bit 0 eccp1if: eccp1 interrupt flag bit (1) capture mode: 1 = a tmr1 (tmr3) register capture occurred (must be cleared in software) 0 = no tmr1 (tmr3) register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode. note 1: this bit is only available on pic18f4x8 devices. for pic18f2x8 devices, this bit is unimplemented and reads as ? 0 ?. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 84 ? 2006 microchip technology inc. register 8-6: pir3: peripheral interrupt request (flag) register 3 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 irxif wakif errif txb2if txb1if txb0if rxb1if rxb0if bit 7 bit 0 bit 7 irxif: invalid message received interrupt flag bit 1 = an invalid message has occurred on the can bus 0 = an invalid message has not occurred on the can bus bit 6 wakif: bus activity wake-up interrupt flag bit 1 = activity on the can bus has occurred 0 = activity on the can bus has not occurred bit 5 errif: can bus error interrupt flag bit 1 = an error has occurred in the can module (multiple sources) 0 = an error has not occurred in the can module bit 4 txb2if: transmit buffer 2 interrupt flag bit 1 = transmit buffer 2 has completed transmission of a message and may be reloaded 0 = transmit buffer 2 has not completed transmission of a message bit 3 txb1if: transmit buffer 1 interrupt flag bit 1 = transmit buffer 1 has completed transmission of a message and may be reloaded 0 = transmit buffer 1 has not completed transmission of a message bit 2 txb0if: transmit buffer 0 interrupt flag bit 1 = transmit buffer 0 has completed transmission of a message and may be reloaded 0 = transmit buffer 0 has not completed transmission of a message bit 1 rxb1if: receive buffer 1 interrupt flag bit 1 = receive buffer 1 has received a new message 0 = receive buffer 1 has not received a new message bit 0 rxb0if: receive buffer 0 interrupt flag bit 1 = receive buffer 0 has received a new message 0 = receive buffer 0 has not received a new message legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 85 pic18fxx8 8.3 pie registers the peripheral interrupt enable (pie) registers contain the individual enable bits for the peripheral interrupts (register 8-7 through register 8-9). due to the number of peripheral interrupt sources, there are three periph- eral interrupt enable registers (pie1, pie2, pie3). when ipen is clear, the peie bit must be set to enable any of these peripheral interrupts. register 8-7: pie1: peripheral interrupt enable register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie bit 7 bit 0 bit 7 pspie: parallel slave port read/write interrupt enable bit (1) 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt bit 6 adie : a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5 rcie : usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4 txie : usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3 sspie : master synchronous serial port interrupt enable bit 1 = enables the mssp interrupt 0 = disables the mssp interrupt bit 2 ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1 tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie : tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt note 1: this bit is only available on pic18f4x8 devices. for pic18f2x8 devices, this bit is unimplemented and reads as ? 0 ?. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 86 ? 2006 microchip technology inc. register 8-8: pie2: peripheral interrupt enable register 2 u-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?cmie (1) ? eeie bclie lvdie tmr3ie eccp1ie (1) bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 cmie: comparator interrupt enable bit (1) 1 = enables the comparator interrupt 0 = disables the comparator interrupt bit 5 unimplemented: read as ? 0 ? bit 4 eeie : eeprom write interrupt enable bit 1 = enabled 0 =disabled bit 3 bclie : bus collision interrupt enable bit 1 = enabled 0 =disabled bit 2 lvdie : low-voltage detect interrupt enable bit 1 = enabled 0 =disabled bit 1 tmr3ie : tmr3 overflow interrupt enable bit 1 = enables the tmr3 overflow interrupt 0 = disables the tmr3 overflow interrupt bit 0 eccp1ie : eccp1 interrupt enable bit (1) 1 = enables the eccp1 interrupt 0 = disables the eccp1 interrupt note 1: this bit is only available on pic18f4x8 devices. for pic18f2x8 devices, this bit is unimplemented and reads as ? 0 ?. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 87 pic18fxx8 register 8-9: pie3: peripheral interrupt enable register 3 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 irxie wakie errie txb2ie txb1ie txb0ie rxb1ie rxb0ie bit 7 bit 0 bit 7 irxie: invalid can message received interrupt enable bit 1 = enables the invalid can message received interrupt 0 = disables the invalid can message received interrupt bit 6 wakie: bus activity wake-up interrupt enable bit 1 = enables the bus activity wake-up interrupt 0 = disables the bus activity wake-up interrupt bit 5 errie: can bus error interrupt enable bit 1 = enables the can bus error interrupt 0 = disables the can bus error interrupt bit 4 txb2ie: transmit buffer 2 interrupt enable bit 1 = enables the transmit buffer 2 interrupt 0 = disables the transmit buffer 2 interrupt bit 3 txb1ie: transmit buffer 1 interrupt enable bit 1 = enables the transmit buffer 1 interrupt 0 = disables the transmit buffer 1 interrupt bit 2 txb0ie: transmit buffer 0 interrupt enable bit 1 = enables the transmit buffer 0 interrupt 0 = disables the transmit buffer 0 interrupt bit 1 rxb1ie: receive buffer 1 interrupt enable bit 1 = enables the receive buffer 1 interrupt 0 = disables the receive buffer 1 interrupt bit 0 rxb0ie: receive buffer 0 interrupt enable bit 1 = enables the receive buffer 0 interrupt 0 = disables the receive buffer 0 interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 88 ? 2006 microchip technology inc. 8.4 ipr registers the interrupt priority (ipr) registers contain the individ- ual priority bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt priority registers (ipr1, ipr2 and ipr3). the operation of the priority bits requires that the interrupt priority enable bit (ipen) be set. register 8-10: ipr1: peripheral interrupt priority register 1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip bit 7 bit 0 bit 7 pspip: parallel slave port read/write interrupt priority bit (1) 1 =high priority 0 = low priority bit 6 adip : a/d converter interrupt priority bit 1 =high priority 0 = low priority bit 5 rcip : usart receive interrupt priority bit 1 =high priority 0 = low priority bit 4 txip : usart transmit interrupt priority bit 1 =high priority 0 = low priority bit 3 sspip : master synchronous serial port interrupt priority bit 1 =high priority 0 = low priority bit 2 ccp1ip : ccp1 interrupt priority bit 1 = high priority 0 = low priority bit 1 tmr2ip : tmr2 to pr2 match interrupt priority bit 1 =high priority 0 = low priority bit 0 tmr1ip : tmr1 overflow interrupt priority bit 1 = high priority 0 = low priority note 1: this bit is only available on pic18f4x8 devices. for pic18f2x8 devices, this bit is unimplemented and reads as ? 0 ?. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 89 pic18fxx8 register 8-11: ipr2: peripheral interrupt priority register 2 u-0 r/w-1 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ?cmip (1) ? eeip bclip lvdip tmr3ip eccp1ip (1) bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 cmip: comparator interrupt priority bit (1) 1 =high priority 0 = low priority bit 5 unimplemented: read as ? 0 ? bit 4 eeip : eeprom write interrupt priority bit 1 =high priority 0 = low priority bit 3 bclip : bus collision interrupt priority bit 1 =high priority 0 = low priority bit 2 lvdip : low-voltage detect interrupt priority bit 1 =high priority 0 = low priority bit 1 tmr3ip : tmr3 overflow interrupt priority bit 1 =high priority 0 = low priority bit 0 eccp1ip : eccp1 interrupt priority bit (1) 1 =high priority 0 = low priority note 1: this bit is only available on pic18f4x8 devices. for pic18f2x8 devices, this bit is unimplemented and reads as ? 0 ?. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 90 ? 2006 microchip technology inc. register 8-12: ipr3: peripheral interrupt priority register 3 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 irxip wakip errip txb2ip txb1ip txb0ip rxb1ip rxb0ip bit 7 bit 0 bit 7 irxip: invalid message received interrupt priority bit 1 =high priority 0 = low priority bit 6 wakip: bus activity wake-up interrupt priority bit 1 =high priority 0 = low priority bit 5 errip: can bus error interrupt priority bit 1 =high priority 0 = low priority bit 4 txb2ip: transmit buffer 2 interrupt priority bit 1 =high priority 0 = low priority bit 3 txb1ip: transmit buffer 1 interrupt priority bit 1 =high priority 0 = low priority bit 2 txb0ip: transmit buffer 0 interrupt priority bit 1 =high priority 0 = low priority bit 1 rxb1ip: receive buffer 1 interrupt priority bit 1 =high priority 0 = low priority bit 0 rxb0ip: receive buffer 0 interrupt priority bit 1 =high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 91 pic18fxx8 8.5 rcon register the reset control (rcon) register contains the ipen bit which is used to enable prioritized interrupts. the functions of the other bits in this register are discussed in more detail in section 4.14 ?rcon register? . register 8-13: rcon: reset control register r/w-0 u-0 u-0 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen ? ?ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16cxxx compatibility mode) bit 6-5 unimplemented: read as ? 0 ? bit 4 ri : reset instruction flag bit for details of bit operation, see register 4-3. bit 3 to : watchdog time-out flag bit for details of bit operation, see register 4-3. bit 2 pd : power-down detection flag bit for details of bit operation, see register 4-3. bit 1 por : power-on reset status bit for details of bit operation, see register 4-3. bit 0 bor : brown-out reset status bit for details of bit operation, see register 4-3. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 92 ? 2006 microchip technology inc. 8.6 int interrupts external interrupts on the rb0/int0, rb1/int1 and rb2/cantx/int2 pins are edge triggered: either rising if the corresponding intedgx bit is set in the intcon2 register, or falling if the intedgx bit is clear. when a valid edge appears on the rbx/intx pin, the corresponding flag bit intxif is set. this interrupt can be disabled by clearing the corresponding enable bit intxie. flag bit intxif must be cleared in software in the interrupt service routine before re-enabling the interrupt. all external interrupts (int0, int1 and int2) can wake-up the processor from sleep if bit intxie was set prior to going into sleep. if the global interrupt enable bit, gie, is set, the processor will branch to the interrupt vector following wake-up. interrupt priority for int1 and int2 is determined by the value contained in the interrupt priority bits int1ip (intcon3<6>) and int2ip (intcon3<7>). there is no priority bit associated with int0; it is always a high priority interrupt source. 8.7 tmr0 interrupt in 8-bit mode (which is the default), an overflow (ffh 00h) in the tmr0 register will set flag bit tmr0if. in 16-bit mode, an overflow (ffffh 0000h) in the tmr0h:tmr0l registers will set flag bit tmr0if. the interrupt can be enabled/disabled by setting/clearing enable bit tmr0ie (intcon register). interrupt priority for timer0 is determined by the value contained in the interrupt priority bit tmr0ip (intcon2 register). see section 11.0 ?timer0 module? for further details. 8.8 portb interrupt-on-change an input change on portb<7:4> sets flag bit rbif (intcon register). the interrupt can be enabled/ disabled by setting/clearing enable bit rbie (intcon register). interrupt priority for portb interrupt-on- change is determined by the value contained in the interrupt priority bit rbip (intcon2 register). 8.9 context saving during interrupts during an interrupt, the return pc value is saved on the stack. additionally, the wreg, status and bsr registers are saved on the fast return stack. if a fast return from interrupt is not used (see section 4.3 ?fast register stack? ), the user may need to save the wreg, status and bsr registers in software. depend- ing on the user?s application, other registers may also need to be saved. example 8-1 saves and restores the wreg, status and bsr registers during an interrupt service routine. example 8-1: saving status, wreg and bsr registers in ram movwf w_temp ; w_temp is in low access bank movff status, status_temp ; status_temp located anywhere movff bsr, bsr_temp ; bsr located anywhere ; ; user isr code ; movff bsr_temp, bsr ; restore bsr movf w_temp, w ; restore wreg movff status_temp, status ; restore status ? 2006 microchip technology inc. ds41159e-page 93 pic18fxx8 9.0 i/o ports depending on the device selected, there are up to five general purpose i/o ports available on pic18fxx8 devices. some pins of the i/o ports are multiplexed with an alternate function from the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. each port has three registers for its operation: ? tris register (data direction register) ? port register (reads the levels on the pins of the device) ? lat register (output latch) the data latch (lat register) is useful for read-modify- write operations on the value that the i/o pins are driving. 9.1 porta, trisa and lata registers porta is a 7-bit wide, bidirectional port. the corre- sponding data direction register is trisa. setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). on a power-on reset, these pins are configured as inputs and read as ? 0 ?. reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. read-modify-write operations on the lata register read and write the latched output value for porta. the ra4 pin is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the ra4/ t0cki pin is a schmitt trigger input and an open-drain output. all other ra port pins have ttl input levels and full cmos output drivers. the other porta pins are multiplexed with analog inputs and the analog v ref + and v ref - inputs. the operation of each pin is selected by clearing/setting the control bits in the adcon1 register (a/d control register 1). on a power-on reset, these pins are configured as analog inputs and read as ? 0 ?. the trisa register controls the direction of the ra pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set, when using them as analog inputs. example 9-1: initializing porta note: on a power-on reset, ra5 and ra3:ra0 are configured as analog inputs and read as ? 0 ?. ra6 and ra4 are configured as digital inputs. clrf porta ; initialize porta by ; clearing output data latches clrf lata ; alternate method to clear ; output data latches movlw 07h ; configure a/d movwf adcon1 ; for digital inputs movlw 0cfh ; value used to initialize ; data direction movwf trisa ; set ra3:ra0 as inputs, ; ra5:ra4 as outputs pic18fxx8 ds41159e-page 94 ? 2006 microchip technology inc. figure 9-1: ra3:ra0 and ra5 pins block diagram figure 9-2: ra4/t0cki pin block diagram figure 9-3: osc2/clko/ra6 pin block diagram data bus p n wr lata wr trisa data latch tris latch rd trisa rd porta v ss v dd i/o pin (1) note 1: i/o pins have diode protection to v dd and v ss . analog input mode ttl input buffer to a/d converter and lvd modules rd lata or wr porta ss input (ra5 only) q d q ck q d q ck qd en data bus wr trisa rd porta data latch tris latch rd trisa schmitt trigger input buffer n v ss i/o pin (1) tmr0 clock input note 1: i/o pin has diode protection to v ss only. q d q ck q d q ck qd en rd lata wr lata or wr porta ttl input buffer data bus p n wr porta wr trisa data latch tris latch rd trisa rd porta v ss v dd oscillator circuit from osc1 1 0 (f osc = 101 , 111 ) data latch clko (f osc /4) osc2/clko ra6 pin (2) (f osc = 100 , schmitt trigger input buffer (f osc = 110 , 100 ) q d q ck q d q ck qd en 101 , 110 , 111 ) note 1: clko is 1/4 of f osc . 2: i/o pin has diode protection to v dd and v ss . ? 2006 microchip technology inc. ds41159e-page 95 pic18fxx8 table 9-1: porta functions table 9-2: summary of registers associated with porta name bit# buffer function ra0/an0/cv ref bit 0 ttl input/output, analog input or analog comparator voltage reference output. ra1/an1 bit 1 ttl input/output or analog input. ra2/an2/v ref - bit 2 ttl input/output, analog input or v ref -. ra3/an3/v ref + bit 3 ttl input/output, analog input or v ref +. ra4/t0cki bit 4 st/od input/output, external clock input for timer0, output is open-drain type. ra5/an4/ss/ lvdin bit 5 ttl input/output, analog input, slave select input for synchronous serial port or low-voltage detect input. osc2/clko/ra6 bit 6 ttl oscillator clock output or input/output. legend: ttl = ttl input, st = schmitt trigger input, od = open-drain name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets porta ? ra6 ra5 ra4 ra3 ra2 ra1 ra0 -00x 0000 -uuu uuuu lata ? latch a data output register -xxx xxxx -uuu uuuu trisa ? porta data direction register -111 1111 -111 1111 adcon1 adfm adcs2 ? ? pcfg3 pcfg2 pcfg1 pcfg0 00-- 0000 uu-- uuuu legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by porta. pic18fxx8 ds41159e-page 96 ? 2006 microchip technology inc. 9.2 portb, trisb and latb registers portb is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisb. setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the latb register, read and write the latched output value for portb. example 9-2: initializing portb each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is performed by clearing bit rbpu (intcon2 register). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. four of the portb pins (rb7:rb4) have an interrupt- on-change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt- on-change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?mismatch? outputs of rb7:rb4 are ored together to generate the rb port change interrupt with flag bit rbif (intcon register). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb (except with the movff instruction). this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. clrf portb ; initialize portb by ; clearing output ; data latches clrf latb ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisb ; set rb3:rb0 as inputs ; rb5:rb4 as outputs ; rb7:rb6 as inputs note 1: while in low-voltage icsp mode, the rb5 pin can no longer be used as a general purpose i/o pin and should not be held low during normal operation to protect against inadvertent icsp mode entry. 2: when using low-voltage icsp program- ming (lvp), the pull-up on rb5 becomes disabled. if trisb bit 5 is cleared, thereby setting rb5 as an output, latb bit 5 must also be cleared for proper operation. ? 2006 microchip technology inc. ds41159e-page 97 pic18fxx8 figure 9-4: rb7:rb4 pins block diagram figure 9-5: rb1:rb0 pins block diagram data latch from other rbpu (2) p v dd i/o pin (1) q d ck q d ck qd en qd en data bus wr latb wr trisb set rbif tris latch rd trisb rd portb rb7:rb4 pins weak pull-up latch ttl input buffer st buffer rbx/intx q3 q1 rd latb or wr portb note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2 register). data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rbx/intx i/o pin (1) ttl input buffer schmitt trigger buffer tris latch note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2 register). pic18fxx8 ds41159e-page 98 ? 2006 microchip technology inc. figure 9-6: rb2/cantx/int2 pin block diagram figure 9-7: rb3/canrx pin block diagram data latch tris latch rd trisb p v ss q d q ck q d q ck qd en n v dd 0 1 rd portb wr trisb data bus rb2/cantx/ cantx endrhi opmode2:opmode0 = 000 schmitt trigger rd latb wr portb or wr latb note 1: i/o pin has diode protection to v dd and v ss . int2 pin (1) data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr latb or portb wr trisb rd trisb rd portb weak pull-up rb3 or canrx i/o pin (1) ttl input buffer schmitt trigger buffer tris latch rd latb cancon<7:5> . note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2<7>). ? 2006 microchip technology inc. ds41159e-page 99 pic18fxx8 table 9-3: portb functions table 9-4: summary of registers associated with portb name bit# buffer function rb0/int0 bit 0 ttl/st (1) input/output pin or external interrupt 0 input. internal software programmable weak pull-up. rb1/int1 bit 1 ttl/st (1) input/output pin or external interrupt 1 input. internal software programmable weak pull-up. rb2/cantx/ int2 bit 2 ttl/st (1) input/output pin, can bus transmit pin or external interrupt 2 input. internal software programmable weak pull-up. rb3/canrx bit 3 ttl input/output pin or can bus receive pin. internal software programmable weak pull-up. rb4 bit 4 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb5/pgm bit 5 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. low-voltage serial programming enable. rb6/pgc bit 6 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming clock. rb7/pgd bit 7 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu latb latb data output register xxxx xxxx uuuu uuuu trisb portb data direction register 1111 1111 1111 1111 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u intcon2 rbpu intedg0 intedg1 ? ? tmr0ip ?rbip 111- -1-1 111- -1-1 intcon3 int2ip int1ip ? int2ie int1ie ? int2if int1if 11-0 0-00 11-1 0-00 legend: x = unknown, u = unchanged. shaded cells are not used by portb. pic18fxx8 ds41159e-page 100 ? 2006 microchip technology inc. 9.3 portc, trisc and latc registers portc is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisc. setting a trisc bit (= 1 ) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the latc register, read and write the latched output value for portc. portc is multiplexed with several peripheral functions (table 9-5). portc pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. the user should refer to the corresponding peripheral section for the correct tris bit settings. the pin override value is not loaded into the tris register. this allows read-modify-write of the tris register, without concern due to peripheral overrides. example 9-3: initializing portc figure 9-8: portc block diagram (peripheral output override) clrf portc ; initialize portc by ; clearing output ; data latches clrf latc ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisc ; set rc3:rc0 as inputs ; rc5:rc4 as outputs ; rc7:rc6 as inputs peripheral out select data bus wr latc wr trisc data latch tris latch rd trisc q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss rd portc peripheral data in i/o pin (1) or wr portc rd latc schmitt trigger note 1: i/o pins have diode protection to v dd and v ss . tris override peripheral enable tris override pin override peripheral rc0 yes timer1 oscillator for timer1/timer3 rc1 yes timer1 oscillator for timer1/timer3 rc2 no ? rc3 yes spi?/i 2 c? master clock rc4 yes i 2 c data out rc5 yes spi data out rc6 yes usart async xmit, sync clock rc7 yes usart sync data out ? 2006 microchip technology inc. ds41159e-page 101 pic18fxx8 table 9-5: portc functions table 9-6: summary of registers associated with portc name bit# buffer type function rc0/t1oso/t1cki bit 0 st input/output port pin, timer1 oscillator output or timer1/timer3 clock input. rc1/t1osi bit 1 st input/output port pin or timer1 oscillator input. rc2/ccp1 bit 2 st input/output port pin or capture 1 input/compare 1 output/ pwm1 output. rc3/sck/scl bit 3 st input/output port pin or synchronous serial clock for spi?/i 2 c?. rc4/sdi/sda bit 4 st input/output port pin or spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit 5 st input/output port pin or synchronous serial port data output. rc6/tx/ck bit 6 st input/output port pin, addressable usart asynchronous transmit or addressable usart synchronous clock. rc7/rx/dt bit 7 st input/output port pin, addressable usart asynchronous receive or addressable usart synchronous data. legend: st = schmitt trigger input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu latc latc data output register xxxx xxxx uuuu uuuu trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged pic18fxx8 ds41159e-page 102 ? 2006 microchip technology inc. 9.4 portd, trisd and latd registers portd is an 8-bit wide, bidirectional port. the corre- sponding data direction register for the port is trisd. setting a trisd bit (= 1 ) will make the corresponding portd pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisd bit (= 0 ) will make the corresponding portd pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the latd register read and write the latched output value for portd. portd uses schmitt trigger input buffers. each pin is individually configurable as an input or output. portd can be configured as an 8-bit wide, micro- processor port (parallel slave port or psp) by setting the control bit pspmode (trise<4>). in this mode, the input buffers are ttl. see section 10.0 ?parallel slave port? for additional information. portd is also multiplexed with the analog comparator module and the eccp module. example 9-4: initializing portd figure 9-9: portd block di agram in i/o port mode note: this port is only available on the pic18f448 and pic18f458. clrf portd ; initialize portd by ; clearing output ; data latches clrf latd ; alternate method ; to clear output ; data latches movlw 07h ; comparator off movwf cmcon movlw 0cfh ; value used to ; initialize data ; direction movwf trisd ; set rd3:rd0 as inputs ; rd5:rd4 as outputs ; rd7:rd6 as inputs port/psp select data bus wr latd wr trisd data latch tris latch rd trisd q d q ck qd en q d q ck p n v dd vss rd portd rd0/psp0/ or portd rd latd schmitt trigger note 1: i/o pins have diode protection to v dd and v ss . psp data out psp write psp read c1in+ c1in+ pin (1) ? 2006 microchip technology inc. ds41159e-page 103 pic18fxx8 table 9-7: portd functions table 9-8: summary of registers associated with portd name bit# buffer type function rd0/psp0/c1in+ bit 0 st/ttl (1) input/output port pin, parallel slave port bit 0 or c1in+ comparator input. rd1/psp1/c1in- bit 1 st/ttl (1) input/output port pin, parallel slave port bit 1 or c1in- comparator input. rd2/psp2/c2in+ bit 2 st/ttl (1) input/output port pin, parallel slave port bit 2 or c2in+ comparator input. rd3/psp3/c2in- bit 3 st/ttl (1) input/output port pin, parallel slave port bit 3 or c2in- comparator input. rd4/psp4/eccp1/p1a bit 4 st/ttl (1) input/output port pin, parallel slave port bit 4 or eccp1/p1a pin. rd5/psp5/p1b bit 5 st/ttl (1) input/output port pin, parallel slave port bit 5 or p1b pin. rd6/psp6/p1c bit 6 st/ttl (1) input/output port pin, parallel slave port bit 6 or p1c pin. rd7/psp7/p1d bit 7 st/ttl (1) input/output port pin, parallel slave port bit 7 or p1d pin. legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu latd latd data output register xxxx xxxx uuuu uuuu trisd portd data direction register 1111 1111 1111 1111 trise ibf obf ibov pspmode ? trise2 trise1 trise0 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by portd. pic18fxx8 ds41159e-page 104 ? 2006 microchip technology inc. 9.5 porte, trise and late registers porte is a 3-bit wide, bidirectional port. porte has three pins (re0/an5/rd , re1/an6/wr /c1out and re2/an7/cs /c2out) which are individually config- urable as inputs or outputs. these pins have schmitt trigger input buffers. read-modify-write operations on the late register, read and write the latched output value for porte. the corresponding data direction register for the port is trise. setting a trise bit (= 1 ) will make the corresponding porte pin an input (i.e., put the corre- sponding output driver in a high-impedance mode). clearing a trise bit (= 0 ) will make the corresponding porte pin an output (i.e., put the contents of the output latch on the selected pin). the trise register also controls the operation of the parallel slave port through the control bits in the upper half of the register. these are shown in register 9-1. when the parallel slave port is active, the porte pins function as its control inputs. for additional details, refer to section 10.0 ?parallel slave port? . porte pins are also multiplexed with inputs for the a/d converter and outputs for the analog comparators. when selected as an analog input, these pins will read as ? 0 ?s. direction bits trise<2:0> control the direction of the re pins, even when they are being used as analog inputs. the user must make sure to keep the pins configured as inputs when using them as analog inputs. example 9-5: initializing porte figure 9-10: porte block diagram note: this port is only available on the pic18f448 and pic18f458. clrf porte ; initialize porte by ; clearing output ; data latches clrf late ; alternate method ; to clear output ; data latches movlw 03h ; value used to ; initialize data ; direction movwf trise ; set re1:re0 as inputs ; re2 as an output ; (re4=0 - pspmode off) peripheral out select data bus wr late wr trise data latch tris latch rd trise q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss rd porte peripheral data in i/o pin (1) or wr porte rd late schmitt trigger note 1: i/o pins have diode protection to v dd and v ss . tris override pin override peripheral re0 yes psp re1 yes psp re2 yes psp tris override peripheral enable ? 2006 microchip technology inc. ds41159e-page 105 pic18fxx8 register 9-1: trise register r-0 r-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 ibf obf ibov pspmode ? trise2 trise1 trise0 bit 7 bit 0 bit 7 ibf: input buffer full status bit 1 = a word has been received and waiting to be read by the cpu 0 = no word has been received bit 6 obf : output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5 ibov : input buffer overflow detect bit (in microprocessor mode) 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no overflow occurred bit 4 pspmode : parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3 unimplemented: read as ? 0 ? bit 2 trise2 : re2 direction control bit 1 = input 0 = output bit 1 trise1 : re1 direction control bit 1 = input 0 = output bit 0 trise0 : re0 direction control bit 1 = input 0 = output legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 106 ? 2006 microchip technology inc. table 9-9: porte functions table 9-10: summary of registers associated with porte name bit# buffer type function re0/an5/rd bit 0 st/ttl (1) input/output port pin, analog input or read control input in parallel slave port mode. re1/an6/wr /c1out bit 1 st/ttl (1) input/output port pin, analog input, write control input in parallel slave port mode or comparator 1 output. re2/an7/cs /c2out bit 2 st/ttl (1) input/output port pin, analog input, chip select control input in parallel slave port mode or comparator 2 output. legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets trise ibf obf ibov pspmode ? trise2 trise1 trise0 0000 -111 0000 -111 porte ? ? ? ? ? read porte pin/ write porte data latch ---- -xxx ---- -uuu late ? ? ? ? ? read porte data latch/ write porte data latch ---- -xxx ---- -uuu adcon1 adfm adcs2 ? ? pcfg3 pcfg2 pcfg1 pcfg0 00-- 0000 00-- 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by porte. ? 2006 microchip technology inc. ds41159e-page 107 pic18fxx8 10.0 parallel slave port in addition to its function as a general i/o port, portd can also operate as an 8-bit wide parallel slave port (psp) or microprocessor port. psp operation is controlled by the 4 upper bits of the trise register (register 9-1). setting control bit pspmode (trise<4>) enables psp operation. in slave mode, the port is asynchronously readable and writable by the external world. the psp can directly interface to an 8-bit micro- processor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting the control bit pspmode enables the porte i/o pins to become control inputs for the microprocessor port. when set, port pin re0 is the rd input, re1 is the wr input and re2 is the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be configured as inputs (set). a write to the psp occurs when both the cs and wr lines are first detected low. a read from the psp occurs when both the cs and rd lines are first detected low. the timing for the control signals in write and read modes is shown in figure 10-2 and figure 10-3, respectively. figure 10-1: portd and porte block diagram (parallel slave port) figure 10-2: parallel slave port write waveforms note: the parallel slave port is only available on pic18f4x8 devices. data bus wr latd rdx pin q d ck en qd en rd portd one bit of portd set interrupt flag pspif (pir1<7>) read chip select write rd cs wr ttl ttl ttl ttl or wr portd rd latd data latch note: i/o pins have diode protection to v dd and v ss . porte pins q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd pic18fxx8 ds41159e-page 108 ? 2006 microchip technology inc. figure 10-3: parallel slave port read waveforms table 10-1: registers associated with parallel slave port q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portd port data latch when written; port pins when read xxxx xxxx uuuu uuuu latd latd data output bits xxxx xxxx uuuu uuuu trisd portd data direction bits 1111 1111 1111 1111 porte ? ? ? ? ?re2re1re0 ---- -xxx ---- -000 late late data output bits ---- -xxx ---- -uuu trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the parallel slave port. ? 2006 microchip technology inc. ds41159e-page 109 pic18fxx8 11.0 timer0 module the timer0 module has the following features: ? software selectable as an 8-bit or 16-bit timer/counter ? readable and writable ? dedicated 8-bit software programmable prescaler ? clock source selectable to be external or internal ? interrupt-on-overflow from ffh to 00h in 8-bit mode and ffffh to 0000h in 16-bit mode ? edge select for external clock register 11-1 shows the timer0 control register (t0con). figure 11-1 shows a simplified block diagram of the timer0 module in 8-bit mode and figure 11-2 shows a simplified block diagram of the timer0 module in 16-bit mode. the t0con register is a readable and writable register that controls all the aspects of timer0, including the prescale selection. register 11-1: t0con: timer0 control register note: timer0 is enabled on por. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 bit 7 bit 0 bit 7 tmr0on: timer0 on/off control bit 1 = enables timer0 0 = stops timer0 bit 6 t08bit : timer0 8-bit/16-bit control bit 1 = timer0 is configured as an 8-bit timer/counter 0 = timer0 is configured as a 16-bit timer/counter bit 5 t0cs : timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clko) bit 4 t0se : timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : timer0 prescaler assignment bit 1 = timer0 prescaler is not assigned. timer0 clock input bypasses prescaler. 0 = timer0 prescaler is assigned. timer0 clock input comes from prescaler output. bit 2-0 t0ps2:t0ps0 : timer0 prescaler select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 110 ? 2006 microchip technology inc. figure 11-1: timer0 block diagram in 8-bit mode figure 11-2: timer0 block diagram in 16-bit mode note 1: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. 2: i/o pins have diode protection to v dd and v ss . ra4/t0cki t0se 1 0 1 0 pin (2) t0cs (1) f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) data bus 8 psa t0ps2, t0ps1, t0ps0 set interrupt flag bit tmr0if on overflow 3 t0cki pin (2) t0se 1 0 1 0 t0cs (1) f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) data bus<7:0> 8 psa t0ps2, t0ps1, t0ps0 set interrupt flag bit tmr0if on overflow 3 tmr0 tmr0h high byte 8 8 8 read tmr0l write tmr0l note 1: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. 2: i/o pins have diode protection to v dd and v ss . ? 2006 microchip technology inc. ds41159e-page 111 pic18fxx8 11.1 timer0 operation timer0 can operate as a timer or as a counter. timer mode is selected by clearing the t0cs bit. in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if the tmr0l register is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0l register. counter mode is selected by setting the t0cs bit. in counter mode, timer0 will increment either on every rising or falling edge of pin ra4/t0cki. the increment- ing edge is determined by the timer0 source edge select bit (t0se). clearing the t0se bit selects the rising edge. restrictions on the external clock input are discussed below. when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. 11.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module. the prescaler is not readable or writable. the psa and t0ps2:t0ps0 bits determine the prescaler assignment and prescale ratio. clearing bit psa will assign the prescaler to the timer0 module. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf tmr0 , movwf tmr0 , bsf tmr0 , x .... etc.) will clear the prescaler count. 11.2.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed ?on-the-fly? during program execution). 11.3 timer0 interrupt the tmr0 interrupt is generated when the tmr0 register overflows from ffh to 00h in 8-bit mode or ffffh to 0000h in 16-bit mode. this overflow sets the tmr0if bit. the interrupt can be masked by clearing the tmr0ie bit. the tmr0if bit must be cleared in software by the timer0 module interrupt service routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep since the timer is shut-off during sleep. 11.4 16-bit mode timer reads and writes timer0 can be set in 16-bit mode by clearing the t08bit in t0con. registers tmr0h and tmr0l are used to access the 16-bit timer value. tmr0h is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the high byte of timer0 (refer to figure 11-1). the high byte of the timer0 timer/counter is not directly readable nor writable. tmr0h is updated with the contents of the high byte of timer0 during a read of tmr0l. this provides the ability to read all 16 bits of timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. a write to the high byte of timer0 must also take place through the tmr0h buffer register. timer0 high byte is updated with the contents of the buffered value of tmr0h when a write occurs to tmr0l. this allows all 16 bits of timer0 to be updated at once. table 11-1: registers associated with timer0 note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count but will not change the prescaler assignment. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets tmr0l timer0 module low byte register xxxx xxxx uuuu uuuu tmr0h timer0 module high byte register 0000 0000 0000 0000 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 1111 1111 trisa ? porta data direction register (1) -111 1111 -111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by timer0. note 1: bit 6 of porta, lata and trisa is enabled in ecio and rcio osci llator modes only. in all ot her oscillator modes, it is disabled and reads as ? 0 ?. pic18fxx8 ds41159e-page 112 ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. ds41159e-page 113 pic18fxx8 12.0 timer1 module the timer1 module timer/counter has the following features: ? 16-bit timer/counter (two 8-bit registers: tmr1h and tmr1l) ? readable and writable (both registers) ? internal or external clock select ? interrupt-on-overflow from ffffh to 0000h ? reset from ccp module special event trigger register 12-1 shows the timer1 control register. this register controls the operating mode of the timer1 module, as well as contains the timer1 oscillator enable bit (t1oscen). timer1 can be enabled/ disabled by setting/clearing control bit, tmr1on (t1con register). figure 12-1 is a simplified block diagram of the timer1 module. register 12-1: t1con: timer1 control register note: timer1 is disabled on por. r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer1 in one 16-bit operation 0 = enables register read/write of timer1 in two 8-bit operations bit 6 unimplemented: read as ? 0 ? bit 5-4 t1ckps1:t1ckps0 : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: timer1 oscillator enable bit 1 = timer1 oscillator is enabled 0 = timer1 oscillator is shut-off the oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 t1sync : timer1 external clock input synchronization select bit when tmr1cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr1cs = 0 : this bit is ignored. timer1 uses the internal clock when tmr1cs = 0 . bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t1cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 114 ? 2006 microchip technology inc. 12.1 timer1 operation timer1 can operate in one of these modes: ?as a timer ? as a synchronous counter ? as an asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con register). when tmr1cs is clear, timer1 increments every instruction cycle. when tmr1cs is set, timer1 increments on every rising edge of the external clock input or the timer1 oscillator, if enabled. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored. timer1 also has an internal ?reset input?. this reset can be generated by the ccp module ( section 15.1 ?ccp1 module? ). figure 12-1: timer1 block diagram figure 12-2: timer1 block diagram: 16-bit read/write mode tmr1h tmr1l t1sync tmr1cs t1ckps1:t1ckps0 sleep input f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 tmr1if overflow tmr1 clr ccp special event trigger t1oscen enable oscillator (1) t1osc interrupt flag bit note 1: when enable bit t1oscen is cleared, the inverter and feedback resistor are turned off. this reduces power drain. t1osi t1cki/t1oso timer 1 tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen enable oscillator (1) tmr1if overflow interrupt f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1cki/t1oso t1osi tmr1 flag bit note 1: when enable bit t1oscen is cleared, the inverter and feedbac k resistor are turned off. this reduces power drain. high byte data bus<7:0> 8 tmr1h 8 8 8 read tmr1l write tmr1l special event trigger ? 2006 microchip technology inc. ds41159e-page 115 pic18fxx8 12.2 timer1 oscillator a crystal oscillator circuit is built in between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit t1oscen (t1con register). the oscillator is a low-power oscillator rated up to 50 khz. it will continue to run during sleep. it is primarily intended for a 32 khz crystal. table 12-1 shows the capacitor selection for the timer1 oscillator. the user must provide a software time delay to ensure proper start-up of the timer1 oscillator. 12.3 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, tmr1if (pir registers). this interrupt can be enabled/disabled by setting/clearing tmr1 interrupt enable bit, tmr1ie (pie registers). 12.4 resetting timer1 using a ccp trigger output if the ccp module is configured in compare mode to generate a ?special event trigger? (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer1 and start an a/d conversion (if the a/d module is enabled). timer1 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a special event trigger from ccp1, the write will take precedence. in this mode of operation, the ccpr1h:ccpr1l register pair effectively becomes the period register for timer1. 12.5 timer1 16-bit read/write mode timer1 can be configured for 16-bit reads and writes (see figure 12-2). when the rd16 control bit (t1con register) is set, the address for tmr1h is mapped to a buffer register for the high byte of timer1. a read from tmr1l will load the contents of the high byte of timer1 into the timer1 high byte buffer register. this provides the user with the ability to accurately read all 16 bits of timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, is valid due to a rollover between reads. a write to the high byte of timer1 must also take place through the tmr1h buffer register. timer1 high byte is updated with the contents of tmr1h when a write occurs to tmr1l. this allows a user to write all 16 bits to both the high and low bytes of timer1 at once. the high byte of timer1 is not directly readable or writable in this mode. all reads and writes must take place through the timer1 high byte buffer register. writes to tmr1h do not clear the timer1 prescaler. the prescaler is only cleared on writes to tmr1l. table 12-1: capacitor selection for the alternate oscillator osc type freq c1 c2 lp 32 khz tbd (1) tbd (1) crystal to be tested: 32.768 khz epson c-001r32.768k-a 20 ppm note 1: microchip suggests 33 pf as a starting point in validating the oscillator circuit. 2: higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: capacitor values are for design guidance only. note: the special event triggers from the ccp1 module will not set interrupt flag bit, tmr1if (pir registers). pic18fxx8 ds41159e-page 116 ? 2006 microchip technology inc. table 12-2: registers associated with timer1 as a timer/counter name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 u-uu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the timer1 module. note 1: these registers or register bi ts are not implemented on the pic18f248 and pic18f258 and read as ? 0 ?s. ? 2006 microchip technology inc. ds41159e-page 117 pic18fxx8 13.0 timer2 module the timer2 module timer has the following features: ? 8-bit timer (tmr2 register) ? 8-bit period register (pr2) ? readable and writable (both registers) ? software programmable prescaler (1:1, 1:4, 1:16) ? software programmable postscaler (1:1 to 1:16) ? interrupt on tmr2 match of pr2 ? ssp module optional use of tmr2 output to generate clock shift register 13-1 shows the timer2 control register. timer2 can be shut-off by clearing control bit tmr2on (t2con register) to minimize power consumption. figure 13-1 is a simplified block diagram of the timer2 module. the prescaler and postscaler selection of timer2 are controlled by this register. 13.1 timer2 operation timer2 can be used as the pwm time base for the pwm mode of the ccp module. the tmr2 register is readable and writable and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps1:t2ckps0 (t2con register). the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit tmr2if, pir registers). the prescaler and postscaler counters are cleared when any of the following occurs: ? a write to the tmr2 register ? a write to the t2con register ? any device reset (power-on reset, mclr reset, watchdog timer reset or brown-out reset) tmr2 is not cleared when t2con is written. register 13-1: t2con: timer2 control register note: timer2 is disabled on por. u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6-3 toutps3:toutps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale ? ? ? 1111 = 1:16 postscale bit 2 tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 118 ? 2006 microchip technology inc. 13.2 timer2 interrupt the timer2 module has an 8-bit period register, pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. 13.3 output of tmr2 the output of tmr2 (before the postscaler) is a clock input to the synchronous serial port module which optionally uses it to generate the shift clock. figure 13-1: timer2 block diagram table 13-1: registers associated with timer2 as a timer/counter comparator tmr2 sets flag tmr2 output (1) reset postscaler prescaler pr2 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software se lected by the ssp module as a baud clock. toutps3:toutps0 t2ckps1:t2ckps0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 tmr2 timer2 module register 0000 0000 0000 0000 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the timer2 module. note 1: these registers or register bits are not impl emented on the pic18f248 and pic18f258 and read as ? 0 ?s. ? 2006 microchip technology inc. ds41159e-page 119 pic18fxx8 14.0 timer3 module the timer3 module timer/counter has the following features: ? 16-bit timer/counter (two 8-bit registers: tmr3h and tmr3l) ? readable and writable (both registers) ? internal or external clock select ? interrupt-on-overflow from ffffh to 0000h ? reset from ccp1/eccp1 module trigger figure 14-1 is a simplified block diagram of the timer3 module. register 14-1 shows the timer3 control register. this register controls the operating mode of the timer3 module and sets the ccp1 and eccp1 clock source. register 12-1 shows the timer1 control register. this register controls the operating mode of the timer1 module, as well as contains the timer1 oscillator enable bit (t1oscen) which can be a clock source for timer3. register 14-1: t3con:timer3 control register note: timer3 is disabled on por. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 t3eccp1 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on bit 7 bit 0 bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer3 in one 16-bit operation 0 = enables register read/write of timer3 in two 8-bit operations bit 6,3 t3eccp1:t3ccp1: timer3 and timer1 to ccp1/eccp1 enable bits 1x = timer3 is the clock source for compare/capture ccp1 and eccp1 modules 01 = timer3 is the clock source for compare/capture of eccp1, timer1 is the clock source for compare/capture of ccp1 00 = timer1 is the clock source for compare/capture ccp1 and eccp1 modules bit 5-4 t3ckps1:t3ckps0 : timer3 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 2 t3sync : timer3 external clock input synchronization control bit (not usable if the system clock comes from timer1/timer3.) when tmr3cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr3cs = 0 : this bit is ignored. timer3 uses the internal clock when tmr3cs = 0 . bit 1 tmr3cs: timer3 clock source select bit 1 = external clock input from timer1 oscillator or t1cki (on the rising edge after the first falling edge) 0 = internal clock (f osc /4) bit 0 tmr3on: timer3 on bit 1 = enables timer3 0 = stops timer3 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 120 ? 2006 microchip technology inc. 14.1 timer3 operation timer3 can operate in one of these modes: ?as a timer ? as a synchronous counter ? as an asynchronous counter the operating mode is determined by the clock select bit, tmr3cs (t3con register). when tmr3cs = 0 , timer3 increments every instruc- tion cycle. when tmr3cs = 1 , timer3 increments on every rising edge of the timer1 external clock input or the timer1 oscillator, if enabled. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored. timer3 also has an internal ?reset input?. this reset can be generated by the ccp module ( section 15.1 ?ccp1 module? ). figure 14-1: timer3 block diagram figure 14-2: timer3 block diagram configured in 16-bit read/write mode tmr3h tmr3l t1osc t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen enable oscillator (1) tmr3if overflow interrupt f osc /4 internal clock tmr3on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1oso/ t1osi flag bit note 1: when enable bit t1oscen is cleared, the inverter and feedback re sistor are turned off. this eliminates power drain. t1cki ccp special trigger t3ccpx clr tmr3l t1osc t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen enable oscillator (1) f osc /4 internal clock tmr3on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1oso/ t1osi tmr3 t1cki clr ccp special trigger t3ccpx to timer1 clock input note 1: when the t1oscen bit is cleared, the inverter and feedback resistor are turned off. th is eliminates power drain. tmr3h data bus<7:0> 8 tmr3h 8 8 8 read tmr3l write tmr3l tmr3if overflow interrupt flag bit ? 2006 microchip technology inc. ds41159e-page 121 pic18fxx8 14.2 timer1 oscillator the timer1 oscillator may be used as the clock source for timer3. the timer1 oscillator is enabled by setting the t1oscen bit (t1con register). the oscillator is a low-power oscillator rated up to 50 khz. refer to section 12.0 ?timer1 module? for timer1 oscillator details. 14.3 timer3 interrupt the tmr3 register pair (tmr3h:tmr3l) increments from 0000h to 0ffffh and rolls over to 0000h. the tmr3 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit tmr3if (pir regis- ters). this interrupt can be enabled/disabled by setting/ clearing tmr3 interrupt enable bit, tmr3ie (pie registers). 14.4 resetting timer3 using a ccp trigger output if the ccp module is configured in compare mode to generate a ?special event trigger? (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer3. timer3 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer3 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer3 coincides with a special event trigger from ccp1, the write will take precedence. in this mode of operation, the ccpr1h:ccpr1l register pair becomes the period register for timer3. refer to section 15.0 ?capture/compare/pwm (ccp) modules? for ccp details. table 14-1: registers associated with timer3 as a timer/counter note: the special event triggers from the ccp module will not set interrupt flag bit tmr3if (pir registers). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir2 ? cmif ? eeif bclif lvdif tmr3if eccp1if -0-0 0000 -0-0 0000 pie2 ? cmie ? eeie bclie lvdie tmr3ie eccp1ie -0-0 0000 -0-0 0000 ipr2 ? cmip ? eeip bclip lvdip tmr3ip eccp1ip -1-1 1111 -1-1 1111 tmr3l holding register for the least significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu tmr3h holding register for the most significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 u-uu uuuu t3con rd16 t3eccp1 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the timer1 module. pic18fxx8 ds41159e-page 122 ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. ds41159e-page 123 pic18fxx8 15.0 capture/compare/pwm (ccp) modules the ccp (capture/compare/pwm) module contains a 16-bit register that can operate as a 16-bit capture register, as a 16-bit compare register or as a pwm duty cycle register. the operation of the ccp module is identical to that of the eccp module (discussed in detail in section 16.0 ?enhanced capture/compare/pwm (eccp) module? ) with two exceptions. the ccp module has a capture special event trigger that can be used as a message received time-stamp for the can module (refer to section 19.0 ?can module? for can operation) which the eccp module does not. the eccp module, on the other hand, has enhanced pwm functionality and auto-shutdown capability. aside from these, the operation of the module described in this section is the same as the eccp. the control register for the ccp module is shown in register 15-1. table 15-2 (following page) details the interactions of the ccp and eccp modules. register 15-1: ccp1con: ccp1 control register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dcxb1:dcxb0 : pwm duty cycle bit 1 and bit 0 capture mode: unused. compare mode: unused. pwm mode: these bits are the two lsbs (bit 1 and bit 0) of the 10-bit pwm duty cycle. the upper eight bits (dcx9:dcx2) of the duty cycle are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : ccpx mode select bits 0000 = capture/compare/pwm off (resets ccpx module) 0001 = reserved 0010 = compare mode, toggle output on match (ccpxif bit is set) 0011 = capture mode, can message received (ccp1 only) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, initialize ccp pin low, on compare match force ccp pin high (ccpif bit is set) 1001 = compare mode, initialize ccp pin high, on compare match force ccp pin low (ccpif bit is set) 1010 = compare mode, ccp pin is unaffected (ccpif bit is set) 1011 = compare mode, trigger special event (ccp1if bit is set; ccp resets tmr1 or tmr3 and starts an a/d conversion if the a/d module is enabled) 11xx =pwm mode legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 124 ? 2006 microchip technology inc. 15.1 ccp1 module capture/compare/pwm register1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. all are readable and writable. table 15-1 shows the timer resources of the ccp module modes. table 15-1: ccp1 mode ? timer resource 15.2 capture mode in capture mode, ccpr1h:ccpr1l captures the 16- bit value of the tmr1 or tmr3 register when an event occurs on pin rc2/ccp1. an event is defined as: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge an event is selected by control bits ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the interrupt request flag bit, ccp1if (pir registers), is set. it must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value will be lost. 15.2.1 ccp pin configuration in capture mode, the rc2/ccp1 pin should be configured as an input by setting the trisc<2> bit. 15.2.2 timer1/timer3 mode selection the timers used with the capture feature (either timer1 and/or timer3) must be running in timer mode or syn- chronized counter mode. in asynchronous counter mode, the capture operation may not work. the timer used with each ccp module is selected in the t3con register. table 15-2: interaction of ccp1 and eccp1 modules ccp1 mode timer resource capture compare pwm timer1 or timer3 timer1 or timer3 timer2 note: if the rc2/ccp1 is configured as an out- put, a write to the port can cause a capture condition. ccp1 mode eccp1 mode interaction capture capture tmr1 or tmr3 time base. time base can be different for each ccp. capture compare the compare could be configured for the special event trigger which clears either tmr1 or tmr3, depending upon which time base is used. compare compare the compare(s) could be configured for the special event trigger which clears tmr1 or tmr3, depending upon which time base is used. pwm pwm the pwms will have the same frequency and update rate (tmr2 interrupt). pwm capture none. pwm compare none. ? 2006 microchip technology inc. ds41159e-page 125 pic18fxx8 15.2.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie registers) clear to avoid false interrupts and should clear the flag bit ccp1if, following any such change in operating mode. 15.2.4 ccp1 prescaler there are four prescaler settings specified by bits ccp1m3:ccp1m0. whenever the ccp1 module is turned off, or the ccp1 module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. example 15-1 shows the recom- mended method for switching between capture prescalers. this example also clears the prescaler counter and will not generate the ?false? interrupt. 15.2.5 can message time-stamp the can capture event occurs when a message is received in either of the receive buffers. the can module provides a rising edge to the ccp1 module to cause a capture event. this feature is provided to time-stamp the received can messages. this feature is enabled by setting the cancap bit of the can i/o control register (ciocon<4>). the message receive signal from the can module then takes the place of the events on rc2/ccp1. example 15-1: changing between capture prescalers figure 15-1: capture mode operat ion block diagram clrf ccp1con, f ; turn ccp module off movlw new_capt_ps ; load wreg with the ; new prescaler mode ; value and ccp on movwf ccp1con ; load ccp1con with ; this value note: i/o pins have diode protection to v dd and v ss . ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if (pir1<2>) tmr3 enable qs ccp1con<3:0> ccp1 pin prescaler 1, 4, 16 and edge detect tmr3h tmr3l tmr1 enable t3eccp1 t3ccp1 t3eccp1 t3ccp1 pic18fxx8 ds41159e-page 126 ? 2006 microchip technology inc. 15.3 compare mode in compare mode, the 16-bit ccpr1 and eccpr1 register value is constantly compared against either the tmr1 register pair value or the tmr3 register pair value. when a match occurs, the ccp1 pin can have one of the following actions: ? driven high ?driven low ? toggle output (high-to-low or low-to-high) ? remains unchanged the action on the pin is based on the value of control bits ccp1m3:ccp1m0. at the same time, interrupt flag bit ccp1if is set. 15.3.1 ccp1 pin configuration the user must configure the ccp1 pin as an output by clearing the appropriate trisc bit. 15.3.2 timer1/timer3 mode selection timer1 and/or timer3 must be running in timer mode, or synchronized counter mode, if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 15.3.3 software interrupt mode when generate software interrupt is chosen, the ccp1 pin is not affected. only a ccp interrupt is generated (if enabled). 15.3.4 special event trigger in this mode, an internal hardware trigger is generated, which may be used to initiate an action. the special event trigger output of ccp1 resets either the tmr1 or tmr3 register pair. additionally, the eccp1 special event trigger will start an a/d conversion if the a/d module is enabled. figure 15-2: compare mode operation block diagram note: clearing the ccp1con register will force the ccp1 compare output latch to the default low level. this is not the data latch. note: the special event trigger from the eccp1 module will not set the timer1 or timer3 interrupt flag bits. special event trigger will: reset timer1 or timer3 (but not set timer1 or timer3 interrupt flag bit) set bit go/done which starts an a/d conversion (eccp1 only) note 1: i/o pins have diode protection to v dd and v ss . tmr1h tmr1l tmr3h tmr3l ccpr1h ccpr1l comparator t3eccp1 t3ccp1 qs r output logic special event trigger match ccp1 ccp1con<3:0> mode select output enable 01 set flag bit ccp1if (pir1<2>) ? 2006 microchip technology inc. ds41159e-page 127 pic18fxx8 table 15-3: registers associated with capture, compare, timer1 and timer3 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 trisd portd data direction register 1111 1111 1111 1111 tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 u-uu uuuu ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx uuuu uuuu ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx uuuu uuuu ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 pir2 ? cmif ? eeif bclif lvdif tmr3if eccp1if -0-0 0000 -0-0 0000 pie2 ? cmie ? eeie bclie lvdie tmr3ie eccp1ie -0-0 0000 -0-0 0000 ipr2 ? cmip ? eeip bclip lvdip tmr3ip eccp1ip -1-1 1111 -1-1 1111 tmr3l holding register for the least significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu tmr3h holding register for the most significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu t3con rd16 t3eccp1 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not us ed by capture and timer1. note 1: these registers or register bits are not im plemented on the pic18f248 and pic18f258 and read as ? 0 ?s. pic18fxx8 ds41159e-page 128 ? 2006 microchip technology inc. 15.4 pwm mode in pulse-width modulation (pwm) mode, the ccp1 pin produces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portc data latch, the trisc<2> bit must be cleared to make the ccp1 pin an output. figure 15-3 shows a simplified block diagram of the ccp module in pwm mode. for a step-by-step procedure on how to set up the ccp module for pwm operation, see section 15.4.3 ?setup for pwm operation? . figure 15-3: simplified pwm block diagram a pwm output (figure 15-4) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 15-4: pwm output 15.4.1 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the following formula. equation 15-1: pwm frequency is defined as 1/[pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ?tmr2 is cleared ? the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) ? the pwm duty cycle is latched from ccpr1l into ccpr1h 15.4.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time. equation 15-2: ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double-buffer the pwm duty cycle. this double-buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2, concatenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portc i/o data latch. ccpr1l (master) ccpr1h (slave) comparator tmr2 pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, set ccp1 pin and latch d.c. trisc<2> rc2/ccp1 note 1: 8-bit timer is concatenated with 2-bit internal q clock, or 2 bits of the prescaler, to create 10-bit time base. comparator period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 note: the timer2 postscaler (see section 13.0 ?timer2 module? ) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. pwm period = [(pr2) + 1] ? 4 ? t osc ? (tmr2 prescale value) pwm duty cycle = (ccpr1l:ccp1con<5:4>) ? t osc ? (tmr2 prescale value) ? 2006 microchip technology inc. ds41159e-page 129 pic18fxx8 the maximum pwm resolution (bits) for a given pwm frequency is given by the following equation. equation 15-3: 15.4.3 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 register. 2. set the pwm duty cycle by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisc<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. configure the ccp1 module for pwm operation. table 15-4: example pwm frequencies and resolutions at 40 mhz table 15-5: registers associated with pwm and timer2 note: if the pwm duty cycle value is longer than the pwm period, the ccp1 pin will not be cleared. f osc f pwm --------------- ?? ?? log 2 () log ----------------------------- b i t s = pwm resolution (max) pwm frequency 2.44 khz 9.76 khz 39.06 khz 156.3 khz 312.5 khz 416.6 khz timer prescaler (1, 4, 16) 16 4 1 1 1 1 pr2 value 0ffh 0ffh 0ffh 3fh 1fh 17h maximum resolution (bits) 10 10 10 8 7 5.5 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 trisd portd data direction register 1111 1111 1111 1111 tmr2 timer2 module register 0000 0000 0000 0000 pr2 timer2 module period register 1111 1111 1111 1111 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by pwm and timer2. note 1: these registers or register bits are not im plemented on the pic18f248 and pic18f258 and read as ? 0 ?s. pic18fxx8 ds41159e-page 130 ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. ds41159e-page 131 pic18fxx8 16.0 enhanced capture/ compare/pwm (eccp) module this module contains a 16-bit register which can oper- ate as a 16-bit capture register, a 16-bit compare register or a pwm master/slave duty cycle register. the operation of the eccp module differs from the ccp (discussed in detail in section 15.0 ?capture/ compare/pwm (ccp) modules? ) with the addition of an enhanced pwm module which allows for up to 4 output channels and user selectable polarity. these features are discussed in detail in section 16.5 ?enhanced pwm mode? . the module can also be programmed for automatic shutdown in response to various analog or digital events. the control register for eccp1 is shown in register 16-1. register 16-1: eccp1con: eccp1 control register note: the eccp (enhanced capture/compare/ pwm) module is only available on pic18f448 and pic18f458 devices. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 epwm1m1 epwm1m0 edc1b1 edc1b0 eccp1m3 eccp1m2 eccp1m1 eccp1m0 bit 7 bit 0 bit 7-6 epwm1m<1:0>: pwm output configuration bits if eccp1m<3:2> = 00, 01, 10 : xx = p1a assigned as capture/compare input; p1b, p1c, p1d assigned as port pins if eccp1m<3:2> = 11 : 00 = single output; p1a modulated; p1b, p1c, p1d assigned as port pins 01 = full-bridge output forward; p1d modulated; p1a active; p1b, p1c inactive 10 = half-bridge output; p1a, p1b modulated with deadband control; p1c, p1d assigned as port pins 11 = full-bridge output reverse; p1b modulated; p1c active; p1a, p1d inactive bit 5-4 edc1b<1:0>: pwm duty cycle least significant bits capture mode: unused. compare mode: unused. pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in eccpr1l. bit 3-0 eccp1m<3:0>: eccp1 mode select bits 0000 = capture/compare/pwm off (resets eccp module) 0001 = unused (reserved) 0010 = compare mode, toggle output on match (eccp1if bit is set) 0011 = unused (reserved) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (eccp1if bit is set) 1001 = compare mode, clear output on match (eccp1if bit is set) 1010 = compare mode, eccp1 pin is unaffected (eccp1if bit is set) 1011 = compare mode, trigger special event (eccp1if bit is set; eccp resets tmr1or tmr3 and starts an a/d conversion if the a/d module is enabled) 1100 = pwm mode; p1a, p1c active-high; p1b, p1d active-high 1101 = pwm mode; p1a, p1c active-high; p1b, p1d active-low 1110 = pwm mode; p1a, p1c active-low; p1b, p1d active-high 1111 = pwm mode; p1a, p1c active-low; p1b, p1d active-low legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 132 ? 2006 microchip technology inc. 16.1 eccp1 module enhanced capture/compare/pwm register 1 (eccpr1) is comprised of two 8-bit registers: eccpr1l (low byte) and eccpr1h (high byte). the eccp1con register controls the operation of eccp1; the additional registers, eccpas and eccp1del, control enhanced pwm specific features. all registers are readable and writable. table 16-1 shows the timer resources for the eccp module modes. table 16-2 describes the interactions of the eccp module with the standard ccp module. in pwm mode, the eccp module can have up to four available outputs, depending on which operating mode is selected. these outputs are multiplexed with portd and the parallel slave port. both the operating mode and the output pin assignments are configured by setting pwm output configuration bits, epwm1m1:epwm1m0 (eccp1con<7:6>). the specific pin assignments for the various output modes are shown in table 16-3. table 16-1: eccp1 mode ? timer resource table 16-2: interaction of ccp1 and eccp1 modules table 16-3: pin assignments for various eccp modes eccp1 mode timer resource capture compare pwm timer1 or timer3 timer1 or timer3 timer2 eccp1 mode ccp1 mode interaction capture capture tmr1 or tmr3 time base. time base can be different for each ccp. capture compare the compare could be configured for the special event trigger which clears either tmr1 or tmr3 depending upon which time base is used. compare compare the compare(s) could be configured for the special event trigger which clears tmr1 or tmr3 depending upon which time base is used. pwm pwm the pwms will have the same frequency and update rate (tmr2 interrupt). pwm capture none pwm compare none eccp mode (1) eccp1con configuration rd4 rd5 rd6 rd7 conventional ccp compatible 00xx11xx eccp1 rd<5>, psp<5> rd<6>, psp<6> rd<7>, psp<7> dual output pwm (2) 10xx11xx p1a p1b rd<6>, psp<6> rd<7>, psp<7> quad output pwm (2) x1xx11xx p1a p1b p1c p1d legend: x = don?t care. shaded cells indicate pin assignments not used by eccp in a given mode. note 1: in all cases, the appropriate trisd bits must be cleared to make the corresponding pin an output. 2: in these modes, the psp i/o control for portd is overridden by p1b, p1c and p1d. ? 2006 microchip technology inc. ds41159e-page 133 pic18fxx8 16.2 capture mode the capture mode of the eccp module is virtually identical in operation to that of the standard ccp mod- ule as discussed in section 15.1 ?ccp1 module? . the differences are in the registers and port pins involved: ? the 16-bit capture register is eccpr1 (eccpr1h and eccpr1l); ? the capture event is selected by control bits eccp1m3:eccp1m0 (eccp1con<3:0>); ? the interrupt bits are eccp1ie (pie2<0>) and eccp1if (pir2<0>); and ? the capture input pin is rd4 and its corresponding direction control bit is trisd<4>. other operational details, including timer selection, output pin configuration and software interrupts, are exactly the same as the standard ccp module. 16.2.1 can message time-stamp the special capture event for the reception of can mes- sages ( section 15.2.5 ?can message time-stamp? ) is not available with the eccp module. 16.3 compare mode the compare mode of the eccp module is virtually identical in operation to that of the standard ccp module as discussed in section 15.2 ?capture mode? . the differences are in the registers and port pins as described in section 16.2 ?capture mode? . all other details are exactly the same. 16.3.1 special event trigger except as noted below, the special event trigger output of eccp1 functions identically to that of the standard ccp module. it may be used to start an a/d conversion if the a/d module is enabled. table 16-4: registers associated with enhanced capture, compare, timer1 and timer3 note: the special event trigger from the eccp1 module will not set the timer1 or timer3 interrupt flag bits. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir2 ? cmif ? eeif bclif lvdif tmr3if eccp1if -0-0 0000 -0-0 0000 pie2 ? cmie ? eeie bclie lvdie tmr3ie eccp1ie -0-0 0000 -0-0 0000 ipr2 ? cmip ? eeip bclip lvdip tmr3ip eccp1ip -1-1 1111 -1-1 1111 tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 u-uu uuuu tmr3l holding register for the least significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu tmr3h holding register for the most significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu t3con rd16 t3eccp1 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 uuuu uuuu trisd portd data direction register 1111 1111 1111 1111 eccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu eccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu eccp1con epwm1m1 epwm1m0 edc1b1 edc1b0 eccp1m3 eccp1m2 eccp1m1 eccp1m0 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the eccp module and timer1. pic18fxx8 ds41159e-page 134 ? 2006 microchip technology inc. 16.4 standard pwm mode when configured in single output mode, the eccp module functions identically to the standard ccp module in pwm mode as described in section 15.4 ?pwm mode? . the differences in registers and ports are as described in section 16.2 ?capture mode? . in addition, the two least significant bits of the 10-bit pwm duty cycle value are represented by eccp1con<5:4>. 16.5 enhanced pwm mode the enhanced pwm mode provides additional pwm output options for a broader range of control applica- tions. the module is an upwardly compatible version of the standard ccp module and is modified to provide up to four outputs, designated p1a through p1d. users are also able to select the polarity of the signal (either active-high or active-low). the module?s output mode and polarity are configured by setting the epwm1m1:epwm1m0 and eccp1m3:eccp1m0 bits of the eccp1con register (eccp1con<7:6> and eccp1con<3:0>, respectively). figure 16-1 shows a simplified block diagram of pwm operation. all control registers are double-buffered and are loaded at the beginning of a new pwm cycle (the period boundary when the assigned timer resets) in order to prevent glitches on any of the outputs. the exception is the pwm delay register, eccp1del, which is loaded at either the duty cycle boundary or the boundary period (whichever comes first). because of the buffering, the module waits until the assigned timer resets instead of starting immediately. this means that enhanced pwm waveforms do not exactly match the standard pwm waveforms, but are instead offset by one full instruction cycle (4 t osc ). as before, the user must manually configure the appropriate trisd bits for output. 16.5.1 pwm output configurations the epwm1m<1:0> bits in the eccp1con register allow one of four configurations: ? single output ? half-bridge output ? full-bridge output, forward mode ? full-bridge output, reverse mode the single output mode is the standard pwm mode discussed in section 15.4 ?pwm mode? . the half- bridge and full-bridge output modes are covered in detail in the sections that follow. the general relationship of the outputs in all configurations is summarized in figure 16-2. figure 16-1: simplified block diagram of the enhanced pwm module note: when setting up single output pwm operations, users are free to use either of the processes described in section 15.4.3 ?setup for pwm operation? or section 16.5.8 ?setup for pwm opera- tion? . the latter is more generic, but will work for either single or multi-output pwm. eccpr1l eccpr1h (slave) comparator tmr2 comparator pr2 (note 1) rq s duty cycle registers eccp1con<5:4> clear timer, set eccp1 pin and latch d.c. note: the 8-bit tmr2 register is concatenated with the 2-bit internal q clock, or 2 bits of the prescaler, to create the 10-bit time base. trisd<4> rd4/psp4/eccp1/p1a trisd<5> rd5/psp5/p1b trisd<6> rd6/psp6/p1c trisd<7> rd7/psp7/p1d output controller epwm1m1<1:0> 2 eccp1m<3:0> 4 eccp1del eccp1/p1a p1b p1c p1d ? 2006 microchip technology inc. ds41159e-page 135 pic18fxx8 figure 16-2: pwm output relationships 0 period 00 10 01 11 delay delay signal pr2 + 1 eccp1con <7:6> p1a modulated, active-high p1a modulated, active-low p1a modulated, active-high p1a modulated, active-low p1b modulated, active-high p1b modulated, active-low p1a active, active-high p1a active, active-low p1b inactive, active-high p1b inactive, active-low p1c inactive, active-high p1c inactive, active-low p1d modulated, active-high p1d modulated, active-low p1a inactive, active-high p1a inactive, active-low p1b modulated, active-high p1b modulated, active-low p1c active, active-high p1c active, active-low p1d inactive, active-high p1d inactive, active-low relationships: ? period = 4 * t osc * (pr2 + 1) * (tmr2 prescale value) ? duty cycle = t osc * (ccpr1l<7:0>:ccp1con<5:4>) * (tmr2 prescale value) ? delay = 4 * t osc * eccp1del duty cycle pic18fxx8 ds41159e-page 136 ? 2006 microchip technology inc. 16.5.2 half-bridge mode in the half-bridge output mode, two pins are used as outputs to drive push-pull loads. the rd4/psp4/ eccp1/p1a pin has the pwm output signal, while the rd5/psp5/p1b pin has the complementary pwm output signal (figure 16-3). this mode can be used for half-bridge applications, as shown in figure 16-4, or for full-bridge applications where four power switches are being modulated with two pwm signals. in half-bridge output mode, the programmable dead- band delay can be used to prevent shoot-through current in bridge power devices. the value of register eccp1del dictates the number of clock cycles before the output is driven active. if the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. see section 16.5.4 ?programmable dead-band delay? for more details of the dead-band delay operations. since the p1a and p1b outputs are multiplexed with the portd<4> and portd<5> data latches, the trisd<4> and trisd<5> bits must be cleared to configure p1a and p1b as outputs. figure 16-3: half-bridge pwm output figure 16-4: examples of half-bri dge output mode applications period duty cycle td td (1) p1a (2) p1b (2) td = dead-band delay period (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. 2: output signals are shown as asserted high. pic18f448/458 p1a p1b fet driver fet driver v+ v- load + - + v - + v - fet driver fet driver v+ v- load + - fet driver fet driver pic18f448/458 p1a p1b standard half-bridge circuit (?push-pull?) half-bridge output driving a full-bridge circuit ? 2006 microchip technology inc. ds41159e-page 137 pic18fxx8 16.5.3 full-bridge mode in full-bridge output mode, four pins are used as out- puts; however, only two outputs are active at a time. in the forward mode, pin rd4/psp4/eccp1/p1a is con- tinuously active and pin rd7/psp7/p1d is modulated. in the reverse mode, rd6/psp6/p1c pin is continu- ously active and rd5/psp5/p1b pin is modulated. these are illustrated in figure 16-5. p1a, p1b, p1c and p1d outputs are multiplexed with the portd<4:7> data latches. the trisd<4:7> bits must be cleared to make the p1a, p1b, p1c and p1d pins output. figure 16-5: full-bridge pwm output period duty cycle p1a (2) p1b (2) p1c (2) p1d (2) forward mode (1) period duty cycle p1a (2) p1c (2) p1d (2) p1b (2) reverse mode (1) (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. note 2: output signal is shown as asserted high. pic18fxx8 ds41159e-page 138 ? 2006 microchip technology inc. figure 16-6: example of full-bridge application 16.5.3.1 direction change in full-bridge mode in the full-bridge output mode, the epwm1m1 bit in the eccp1con register allows the user to control the forward/reverse direction. when the application firm- ware changes this direction control bit, the eccp1 module will assume the new direction on the next pwm cycle. the current pwm cycle still continues, however, the non-modulated outputs, p1a and p1c signals, will transition to the new direction t osc , 4 t osc or 16 t osc earlier (for t2ckrs<1:0> = 00 , 01 or 1x , respectively) before the end of the period. during this transition cycle, the modulated outputs, p1b and p1d, will go to the inactive state (figure 16-7). note that in the full-bridge output mode, the eccp module does not provide any dead-band delay. in general, since only one output is modulated at all times, dead-band delay is not required. however, there is a situation where a dead-band delay might be required. this situation occurs when all of the following conditions are true: 1. the direction of the pwm output changes when the duty cycle of the output is at or near 100%. 2. the turn-off time of the power switch, including the power device and driver circuit, is greater than turn-on time. figure 16-8 shows an example where the pwm direction changes from forward to reverse at a near 100% duty cycle. at time t1, the outputs p1a and p1d become inactive, while output p1c becomes active. in this example, since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current flows through power devices qb and qd (see figure 16-6) for the duration of ?t?. the same phenom- enon will occur to power devices qa and qc for pwm direction change from reverse to forward. if changing pwm direction at high duty cycle is required for an application, one of the following requirements must be met: 1. avoid changing pwm output direction at or near 100% duty cycle. 2. use switch drivers that compensate the slow turn off of the power devices. the total turn-off time (t off ) of the power device and the driver must be less than the turn-on time (t on ). pic18f448/458 p1d p1b fet driver fet driver v+ v- load + - fet driver fet driver p1c p1a qd qc qa qb ? 2006 microchip technology inc. ds41159e-page 139 pic18fxx8 figure 16-7: pwm direction change figure 16-8: pwm direction chang e at near 100% duty cycle dc period (1) signal note 1: the direction bit in the eccp1 control register (e ccp1con.epwm1m1) is written any time during the pwm cycle. 2: the p1a and p1c signals switch at intervals of t osc , 4 t osc or 16 t osc , depending on the timer2 prescaler value earlier when changing direction. the modulated p1b and p1d signals are inactive at this time. period (2) p1a (active-high) p1b (active-high) p1c (active-high) p1d (active-high) forward period reverse period (pwm) p1a (1) (pwm) t on (2) t off (3) t = t off ? t on (2,3) p1b (1) p1c (1) p1d (1) external switch d (1) potential shoot-through current (1) note 1: all signals are shown as active-high. 2: t on is the turn-on delay of power switch and driver. 3: t off is the turn-off delay of power switch and driver. external switch c (1) t1 pic18fxx8 ds41159e-page 140 ? 2006 microchip technology inc. 16.5.4 programmable dead-band delay in half-bridge or full-bridge applications, where all power switches are modulated at the pwm frequency at all times, the power switches normally require longer time to turn off than to turn on. if both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches will be on for a short period of time until one switch completely turns off. during this time, a very high current ( shoot-through current ) flows through both power switches, shorting the bridge supply. to avoid this potentially destructive shoot-through current from flowing during switching, turning on the power switch is normally delayed to allow the other switch to completely turn off. in the half-bridge output mode, a digitally programmable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. the delay occurs at the signal transition from the non-active state to the active state. see figure 16-3 for illustration. the eccp1del register (register 16-2) sets the amount of delay. 16.5.5 system implementation when the eccp module is used in the pwm mode, the application hardware must use the proper external pull- up and/or pull-down resistors on the pwm output pins. when the microcontroller powers up, all of the i/o pins are in the high-impedance state. the external pull-up and pull-down resistors must keep the power switch devices in the off state until the microcontroller drives the i/o pins with the proper signal levels, or activates the pwm output(s). 16.5.6 start-up considerations prior to enabling the pwm outputs, the p1a, p1b, p1c and p1d latches may not be in the proper states. enabling the trisd bits for output at the same time with the eccp1 module may cause damage to the power switch devices. the eccp1 module must be enabled in the proper output mode with the trisd bits enabled as inputs. once the eccp1 completes a full pwm cycle, the p1a, p1b, p1c and p1d output latches are properly initialized. at this time, the trisd bits can be enabled for outputs to start driving the power switch devices. the completion of a full pwm cycle is indicated by the tmr2if bit going from a ? 0 ? to a ? 1 ?. 16.5.7 output polarity configuration the eccp1m<1:0> bits in the eccp1con register allow user to choose the logic conventions (asserted high/low) for each of the outputs. the pwm output polarities must be selected before the pwm outputs are enabled. charging the polarity configuration while the pwm outputs are active is not recommended since it may result in unpredictable operation. register 16-2: eccp1del: pwm delay register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 epdc7 epdc6 epdc5 epdc4 epdc3 epdc2 epdc1 epdc0 bit 7 bit 0 bit 7-0 epdc<7:0>: pwm delay count for half-bridge output mode bits number of f osc /4 (t osc * 4) cycles between the p1a transition and the p1b transition. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 141 pic18fxx8 16.5.8 setup for pwm operation the following steps should be taken when configuring the eccp1 module for pwm operation: 1. configure the pwm module: a) disable the eccp1/p1a, p1b, p1c and/or p1d outputs by setting the respective trisd bits. b) set the pwm period by loading the pr2 register. c) set the pwm duty cycle by loading the eccpr1l register and eccp1con<5:4> bits. d) configure the eccp1 module for the desired pwm operation by loading the eccp1con register with the appropriate value. with the eccp1m<3:0> bits, select the active-high/low levels for each pwm output. with the epwm1m<1:0> bits, select one of the available output modes. e) for half-bridge output mode, set the dead- band delay by loading the eccp1del register with the appropriate value. 2. configure and start tmr2: a) clear the tmr2 interrupt flag bit by clearing the tmr2if bit in the pir1 register. b) set the tmr2 prescale value by loading the t2ckps bits (t2con<1:0>). c) enable timer2 by setting the tmr2on bit (t2con<2>) register. 3. enable pwm outputs after a new cycle has started: a) wait until tmr2 overflows (tmr2if bit becomes a ? 1 ?). the new pwm cycle begins here. b) enable the eccp1/p1a, p1b, p1c and/or p1d pin outputs by clearing the respective trisd bits. table 16-5: registers associated with enhanced pwm and timer2 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u rcon ipen ? ? ri to pd por bor 0--1 110q 0--0 011q ipr2 ? cmip ? eeip bclip lvdip tmr3ip eccp1ip -1-1 1111 -1-1 1111 pir2 ? cmif ? eeif bclif lvdif tmr3if eccp1if -0-0 0000 -0-0 0000 pie2 ? cmie ? eeie bclie lvdie tmr3ie eccp1ie -0-0 0000 -0-0 0000 tmr2 timer2 module register 0000 0000 0000 0000 pr2 timer2 module period register 1111 1111 1111 1111 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 trisd portd data direction register 1111 1111 1111 1111 eccpr1h enhanced capture/compare/pwm register 1 high byte xxxx xxxx uuuu uuuu eccpr1l enhanced capture/compare/pwm register 1 low byte xxxx xxxx uuuu uuuu eccp1con epwm1m1 epwm1m0 edc1b1 edc1b0 eccp1m3 eccp1m2 eccp1m1 eccp1m0 0000 0000 0000 0000 eccpas eccpase eccpas2 eccpas1 eccpas0 pssac1 pssac0 pssbd1 pssbd0 0000 0000 0000 0000 eccp1del epdc7 epdc6 epdc5 epdc4 epdc3 epdc2 epdc1 epdc0 0000 0000 uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not us ed by the eccp module. pic18fxx8 ds41159e-page 142 ? 2006 microchip technology inc. 16.6 enhanced ccp auto-shutdown when the eccp is programmed for any of the pwm modes, the output pins associated with its function may be configured for auto-shutdown. auto-shutdown allows the internal output of either of the two comparator modules, or the external interrupt 0, to asynchronously disable the eccp output pins. thus, an external analog or digital event can discontinue an eccp sequence. the comparator out- put(s) to be used is selected by setting the proper mode bits in the eccpas register. to use external interrupt int0 as a shutdown event, int0ie must be set. to use either of the comparator module outputs as a shutdown event, corresponding comparators must be enabled. when a shutdown occurs, the selected output values (pssacn, pssbdn) are written to the eccp port pins. the internal shutdown signal is gated with the outputs and will immediately and asynchronously disable the outputs. if the internal shutdown is still in effect at the time a new cycle begins, that entire cycle is suppressed, thus eliminating narrow, glitchy pulses. the eccpase bit is set by hardware upon a compara- tor event and can only be cleared in software. the eccp outputs can be re-enabled only by clearing the eccpase bit. the auto-shutdown mode can be manually entered by writing a ? 1 ? to the eccpase bit. register 16-3: eccpas: enhanced capture/compare/pwm auto-shutdown control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eccpase eccpas2 eccpas1 eccpas0 pssac1 pssac0 pssbd1 pssbd0 bit 7 bit 0 bit 7 eccpase: eccp auto-shutdown event status bit 0 = eccp outputs enabled, no shutdown event 1 = a shutdown event has occurred, must be reset in software to re-enable eccp bit 6-4 eccpas<2:0>: eccp auto-shutdown bits 000 = no auto-shutdown enabled, comparators have no effect on eccp 001 = comparator 1 output will cause shutdown 010 = comparator 2 output will cause shutdown 011 = either comparator 1 or 2 can cause shutdown 100 =int0 101 = int0 or comparator 1 output 110 = int0 or comparator 2 output 111 = int0 or comparator 1 or comparator 2 output bit 3-2 pssacn: pins a and c shutdown state control bits 00 = drive pins a and c to ? 0 ? 01 = drive pins a and c to ? 1 ? 1x = pins a and c tri-state bit 1-0 pssbdn: pins b and d shutdown state control bits 00 = drive pins b and d to ? 0 ? 01 = drive pins b and d to ? 1 ? 1x = pins b and d tri-state legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 143 pic18fxx8 17.0 master synchronous serial port (mssp) module 17.1 master ssp (mssp) module overview the master synchronous serial port (mssp) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the mssp module can operate in one of two modes: ? serial peripheral interface (spi) ? inter-integrated circuit (i 2 c) - full master mode - slave mode (with general address call) the i 2 c interface supports the following modes in hardware: ?master mode ? multi-master mode ? slave mode 17.2 control registers the mssp module has three associated registers. these include a status register (sspstat) and two control registers (sspcon1 and sspcon2). the use of these registers and their individual configuration bits differ significantly, depending on whether the mssp module is operated in spi or i 2 c mode. additional details are provided under the individual sections. 17.3 spi mode the spi mode allows 8 bits of data to be synchronously transmitted and received simultaneously. all four modes of spi are supported. to accomplish communication, typically three pins are used: ? serial data out (sdo) ? rc5/sdo ? serial data in (sdi) ? rc4/sdi/sda ? serial clock (sck) ? rc3/sck/scl additionally, a fourth pin may be used when in a slave mode of operation: ? slave select (ss ) ? ra5/an4/ss /lvdin figure 17-1 shows the block diagram of the mssp module when operating in spi mode. figure 17-1: mssp block diagram (spi? mode) ( ) read write internal data bus sspsr reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to tx/rx in sspsr tris bit 2 smp:cke rc5/sdo sspbuf reg rc4/sdi/sda ra5/an4/ rc3/sck/ scl ss /lvdin pic18fxx8 ds41159e-page 144 ? 2006 microchip technology inc. 17.3.1 registers the mssp module has four registers for spi mode operation. these are: ? mssp control register 1 (sspcon1) ? mssp status register (sspstat) ? serial receive/transmit buffer (sspbuf) ? mssp shift register (sspsr) ? not directly accessible sspcon1 and sspstat are the control and status registers in spi mode operation. the sspcon1 register is readable and writable. the lower 6 bits of the sspstat are read-only. the upper two bits of the sspstat are read/write. sspsr is the shift register used for shifting data in or out. sspbuf is the buffer register to which data bytes are written to or read from. in receive operations, sspsr and sspbuf together create a double-buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not double- buffered. a write to sspbuf will write to both sspbuf and sspsr. register 17-1: sspstat: mssp status register (spi mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode. bit 6 cke: spi clock edge select bit 1 = transmit occurs on transition from active to idle clock state 0 = transmit occurs on transition from idle to active clock state note: polarity of clock state is set by the ckp bit (sspcon1<4>). bit 5 d/a : data/address bit used in i 2 c mode only. bit 4 p: stop bit used in i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared. bit 3 s: start bit used in i 2 c mode only. bit 2 r/w : read/write information bit used in i 2 c mode only. bit 1 ua: update address bit used in i 2 c mode only. bit 0 bf: buffer full status bit (receive mode only) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 145 pic18fxx8 register 17-2: sspcon1: mssp control register 1 (spi mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit (transmit mode only) 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit spi slave mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode.the user must read the sspbuf even if only transmitting data to avoid setting overflow (must be cleared in software). 0 = no overflow note: in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. bit 5 sspen: synchronous serial port enable bit 1 = enables serial port and configures sck, sdo, sdi and ss as serial port pins 0 = disables serial port and configures these pins as i/o port pins note: when enabled, these pins must be properly configured as input or output. bit 4 ckp: clock polarity select bit 1 = idle state for clock is a high level 0 = idle state for clock is a low level bit 3-0 sspm3:sspm0: synchronous serial port mode select bits 0101 = spi slave mode, clock = sck pin, ss pin control disabled, ss can be used as i/o pin 0100 = spi slave mode, clock = sck pin, ss pin control enabled 0011 = spi master mode, clock = tmr2 output/2 0010 = spi master mode, clock = f osc /64 0001 = spi master mode, clock = f osc /16 0000 = spi master mode, clock = f osc /4 note: bit combinations not specifically listed here are either reserved or implemented in i 2 c mode only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 146 ? 2006 microchip technology inc. 17.3.2 operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspcon1<5:0> and sspstat<7:6>). these control bits allow the following to be specified: ? master mode (sck is the clock output) ? slave mode (sck is the clock input) ? clock polarity (idle state of sck) ? data input sample phase (middle or end of data output time) ? clock edge (output data on rising/falling edge of sck) ? clock rate (master mode only) ? slave select mode (slave mode only) the mssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr until the received data is ready. once the 8 bits of data have been received, that byte is moved to the sspbuf register. then, the buffer full detect bit bf (sspstat<0>) and the interrupt flag bit sspif are set. this double-buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored and the write collision detect bit, wcol (sspcon1<7>), will be set. user software must clear the wcol bit so that it can be determined if the follow- ing write(s) to the sspbuf register completed successfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. buffer full bit, bf (sspstat<0>), indicates when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp interrupt is used to determine when the transmission/reception has com- pleted. the sspbuf must be read and/or written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 17-1 shows the loading of the sspbuf (sspsr) for data transmission. the sspsr is not directly readable or writable and can only be accessed by addressing the sspbuf register. additionally, the mssp status register (sspstat) indicates the various status conditions. example 17-1: loading the sspbuf (sspsr) register loop btfss sspstat, bf ;has data been received(transmit complete)? bra loop ;no movf sspbuf, w ;wreg reg = contents of sspbuf movwf rxdata ;save in user ram, if data is meaningful movf txdata, w ;w reg = contents of txdata movwf sspbuf ;new data to xmit ? 2006 microchip technology inc. ds41159e-page 147 pic18fxx8 17.3.3 enabling spi i/o to enable the serial port, ssp enable bit, sspen (sspcon1<5>), must be set. to reset or reconfigure spi mode, clear the sspen bit, reinitialize the sspcon registers and then, set the sspen bit. this configures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port function, some must have their data direction bits (in the tris register) appropriately programmed as follows: ? sdi is automatically controlled by the spi module ? sdo must have trisc<5> bit cleared ? sck (master mode) must have trisc<3> bit cleared ? sck (slave mode) must have trisc<3> bit set ?ss must have trisa<5> bit set any serial port function that is not desired may be over- ridden by programming the corresponding data direction (tris) register to the opposite value. 17.3.4 typical connection figure 17-2 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sck signal. data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. both processors should be programmed to the same clock polarity (ckp), then both controllers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data transmission: ? master sends data ? slave sends dummy data ? master sends data ? slave sends data ? master sends dummy data ? slave sends data figure 17-2: spi? master/slave connection serial input buffer (sspbuf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi? master sspm3:sspm0 = 00xxb serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi? slave sspm3:sspm0 = 010xb serial clock pic18fxx8 ds41159e-page 148 ? 2006 microchip technology inc. 17.3.5 master mode the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2, figure 17-2) is to broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sdo output could be dis- abled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a ?line activity monitor? mode. the clock polarity is selected by appropriately program- ming the ckp bit (sspcon1<4>). this then, would give waveforms for spi communication as shown in figure 17-3, figure 17-5 and figure 17-6, where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: ?f osc /4 (or t cy ) ?f osc /16 (or 4 ? t cy ) ?f osc /64 (or 16 ? t cy ) ? timer2 output/2 this allows a maximum data rate (at 40 mhz) of 10.00 mbps. figure 17-3 shows the waveforms for master mode. when the cke bit is set, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspbuf is loaded with the received data is shown. figure 17-3: spi? mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit7 sdi sspif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) next q4 cycle after q2 bit 0 ? 2006 microchip technology inc. ds41159e-page 149 pic18fxx8 17.3.6 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched, the sspif interrupt flag bit is set. while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. when a byte is received, the device will wake-up from sleep. before enabling the module in spi slave mode, the clock line must match the proper idle state. the clock line can be observed by reading the sck pin. the idle state is determined by the ckp bit (sspcon1<4>). 17.3.7 slave select synchronization the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspcon1<3:0> = 04h). the pin must not be driven low for the ss pin to function as an input. the data latch must be high. when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. external pull-up/pull-down resistors may be desirable depending on the application. when the spi module resets, the bit counter is forced to ? 0 ?. this can be done by either forcing the ss pin to a high level or clearing the sspen bit. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver, the sdo pin can be configured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function) since it cannot create a bus conflict. figure 17-4: slave synchronization waveform note 1: when the spi is in slave mode with ss pin control enabled (sspcon1<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: if the spi is used in slave mode with cke set, then the ss pin control must be enabled. sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 7 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag bit 0 bit 7 bit 0 next q4 cycle after q2 pic18fxx8 ds41159e-page 150 ? 2006 microchip technology inc. figure 17-5: spi? mode waveform (slave mode with cke = 0 ) figure 17-6: spi? mode waveform (slave mode with cke = 1 ) sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag optional next q4 cycle after q2 sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 1 ) cke = 1 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag not optional next q4 cycle after q2 ? 2006 microchip technology inc. ds41159e-page 151 pic18fxx8 17.3.8 sleep operation in master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from sleep. after the device returns to normal mode, the module will continue to transmit/ receive data. in slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode and data to be shifted into the spi transmit/receive shift register. when all 8 bits have been received, the mssp interrupt flag bit will be set and if enabled, will wake the device from sleep. 17.3.9 effects of a reset a reset disables the mssp module and terminates the current transfer. 17.3.10 bus mode compatibility table 17-1 shows the compatibility between the standard spi modes and the states of the ckp and cke control bits. table 17-1: spi? bus modes there is also an smp bit which controls when the data is sampled. table 17-2: registers associated with spi? operation standard spi mode terminology control bits state ckp cke 0, 0 0 1 0, 1 0 0 1, 0 1 1 1, 1 1 0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 trisc portc data direction register 1111 1111 1111 1111 trisa ? trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 -111 1111 -111 1111 sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the mssp in spi? mode. note 1: these registers or register bits are not implemented on the pic18f248 and pic18f258 and read as ? 0 ?s. pic18fxx8 ds41159e-page 152 ? 2006 microchip technology inc. 17.4 i 2 c mode the mssp module in i 2 c mode fully implements all master and slave functions (including general call support) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master function). the mssp module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. two pins are used for data transfer: ? serial clock (scl) ? rc3/sck/scl ? serial data (sda) ? rc4/sdi/sda the user must configure these pins as inputs or outputs through the trisc<4:3> bits. figure 17-7: mssp block diagram (i 2 c? mode) 17.4.1 registers the mssp module has six registers for i 2 c operation. these are: ? mssp control register 1 (sspcon1) ? mssp control register 2 (sspcon2) ? mssp status register (sspstat) ? serial receive/transmit buffer (sspbuf) ? mssp shift register (sspsr) ? not directly accessible ? mssp address register (sspadd) sspcon1, sspcon2 and sspstat are the control and status registers in i 2 c mode operation. the sspcon1 and sspcon2 registers are readable and writable. the lower 6 bits of the sspstat are read-only. the upper two bits of the sspstat are read/write. sspsr is the shift register used for shifting data in or out. sspbuf is the buffer register to which data bytes are written to or read from. sspadd register holds the slave device address when the ssp is configured in i 2 c slave mode. when the ssp is configured in master mode, the lower seven bits of sspadd act as the baud rate generator reload value. in receive operations, sspsr and sspbuf together create a double-buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not double- buffered. a write to sspbuf will write to both sspbuf and sspsr. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) rc3/sck/ rc4/ shift clock msb sdi/ lsb sda scl ? 2006 microchip technology inc. ds41159e-page 153 pic18fxx8 register 17-3: sspstat: mssp status register (i 2 c mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: slew rate control bit in master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high-speed mode (400 khz) bit 6 cke: smbus select bit in master or slave mode: 1 = enable smbus specific inputs 0 = disable smbus specific inputs bit 5 d/a : data/address bit in master mode: reserved. in slave mode: 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last note: this bit is cleared on reset and when sspen is cleared. bit 3 s: start bit 1 = indicates that a start bit has been detected last 0 = start bit was not detected last note: this bit is cleared on reset and when sspen is cleared. bit 2 r/w : read/write information bit (i 2 c mode only) in slave mode: 1 = read 0 = write note: this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit or not ack bit. in master mode: 1 = transmit is in progress 0 = transmit is not in progress note: oring this bit with sen, rsen, pen, rcen or acken will indicate if the mssp is in idle mode. bit 1 ua: update address bit (10-bit slave mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit in transmit mode: 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty in receive mode: 1 = data transmit in progress (does not include the ack and stop bits), sspbuf is full 0 = data transmit complete (does not include the ac k and stop bits), sspbuf is empty legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 154 ? 2006 microchip technology inc. register 17-4: sspcon1: mssp control register 1 (i 2 c mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit in master transmit mode: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started (must be cleared in software) 0 = no collision in slave transmit mode: 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision in receive mode (master or slave modes): this is a ?don?t care? bit. bit 6 sspov: receive overflow indicator bit in receive mode: 1 = a byte is received while the sspbuf register is still holding the previous byte (must be cleared in software) 0 = no overflow in transmit mode: this is a ?don?t care? bit in transmit mode. bit 5 sspen: synchronous serial port enable bit 1 = enables the serial port and configures the sda and scl pins as the serial port pins 0 = disables serial port and configures these pins as i/o port pins note: when enabled, the sda and scl pins must be properly configured as input or output. bit 4 ckp: sck release control bit in slave mode: 1 = release clock 0 = holds clock low (clock stretch), used to ensure data setup time in master mode: unused in this mode. bit 3-0 sspm3:sspm0: synchronous serial port mode select bits 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1011 = i 2 c firmware controlled master mode (slave idle) 1000 = i 2 c master mode, clock = f osc /(4 * (sspadd + 1)) 0111 = i 2 c slave mode, 10-bit address 0110 = i 2 c slave mode, 7-bit address note: bit combinations not specifically listed here are either reserved or implemented in spi mode only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 155 pic18fxx8 register 17-5: sspcon2: mssp control register 2 (i 2 c mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt acken rcen pen rsen sen bit 7 bit 0 bit 7 gcen: general call enable bit (slave mode only) 1 = enable interrupt when a general call address (0000h) is received in the sspsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (master transmit mode only) 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5 ackdt: acknowledge data bit (master receive mode only) 1 = not acknowledge 0 = acknowledge note: value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. bit 4 acken: acknowledge sequence enable bit (master receive mode only) 1 = initiate acknowledge sequence on sda and scl pins and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (master mode only) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (master mode only) 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enable bit (master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enable/stretch enable bit in master mode: 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle in slave mode: 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is enabled for slave transmit only (legacy mode) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the sspbuf may not be written (or writes to the sspbuf are disabled). pic18fxx8 ds41159e-page 156 ? 2006 microchip technology inc. 17.4.2 operation the mssp module functions are enabled by setting mssp enable bit, sspen (sspcon1<5>). the sspcon1 register allows control of the i 2 c operation. four mode selection bits (sspcon1<3:0>) allow one of the following i 2 c modes to be selected: ?i 2 c master mode, clock = osc/4 (sspadd +1) ?i 2 c slave mode (7-bit address) ?i 2 c slave mode (10-bit address) ?i 2 c slave mode (7-bit address) with start and stop bit interrupts enabled ?i 2 c slave mode (10-bit address) with start and stop bit interrupts enabled ?i 2 c firmware controlled master mode, slave is idle selection of any i 2 c mode with the sspen bit set forces the scl and sda pins to be open-drain, pro- vided these pins are programmed to inputs by setting the appropriate trisc bits. to ensure proper operation of the module, pull-up resistors must be provided externally to the scl and sda pins. 17.4.3 slave mode in slave mode, the scl and sda pins must be config- ured as inputs (trisc<4:3> set). the mssp module will override the input state with the output data when required (slave-transmitter). the i 2 c slave mode hardware will always generate an interrupt on an address match. through the mode select bits, the user can also choose to interrupt on start and stop bits. when an address is matched, or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse and load the sspbuf register with the received value currently in the sspsr register. any combination of the following conditions will cause the mssp module not to give this ack pulse: ? the buffer full bit, bf (sspstat<0>), was set before the transfer was received. ? the overflow bit, sspov (sspcon1<6>), was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir1<3>) is set. the bf bit is cleared by reading the sspbuf register, while bit sspov is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the mssp module, are shown in timing parameter #100 and parameter #101. 17.4.3.1 addressing once the mssp module has been enabled, it waits for a start condition to occur. following the start condition, the 8 bits are shifted into the sspsr register. all incom- ing bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match and the bf and sspov bits are clear, the following events occur: 1. the sspsr register value is loaded into the sspbuf register. 2. the buffer full bit bf is set. 3. an ack pulse is generated. 4. mssp interrupt flag bit, sspif (pir1<3>), is set (interrupt is generated if enabled) on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave. the five most significant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address, the first byte would equal ? 11110 a9 a8 0 ?, where ? a9 ? and ? a8 ? are the two msbs of the address. the sequence of events for 10-bit address is as follows, with steps 7 through 9 for the slave-transmitter: 1. receive first (high) byte of address (bits sspif, bf and bit ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf and ua are set). 5. update the sspadd register with the first (high) byte of address. if match releases scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif. ? 2006 microchip technology inc. ds41159e-page 157 pic18fxx8 17.4.3.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register and the sda line is held low (ack ). when the address byte overflow condition exists, then the no acknowledge (ack ) pulse is given. an overflow condition is defined as either bit bf (sspstat<0>) is set or bit sspov (sspcon1<6>) is set. an mssp interrupt is generated for each data transfer byte. flag bit sspif (pir1<3>) must be cleared in software. the sspstat register is used to determine the status of the byte. if sen is enabled (sspcon2<0> = 1 ), rc3/sck/scl will be held low (clock stretch) following each data transfer. the clock must be released by setting bit ckp (sspcon1<4>). see section 17.4.4 ?clock stretching? for more detail. 17.4.3.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit and pin rc3/sck/scl is held low regardless of sen (see section 17.4.4 ?clock stretching? for more detail). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then, pin rc3/ sck/scl should be enabled by setting bit ckp (sspcon1<4>). the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 17-9). the ack pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. if the sda line is high (not ack ), then the data transfer is complete. in this case, when the ack is latched by the slave, the slave logic is reset (resets sspstat regis- ter) and the slave monitors for another occurrence of the start bit. if the sda line was low (ack ), the next transmit data must be loaded into the sspbuf register. again, pin rc3/sck/scl must be enabled by setting bit ckp. an mssp interrupt is generated for each data transfer byte. the sspif bit must be cleared in software and the sspstat register is used to determine the status of the byte. the sspif bit is set on the falling edge of the ninth clock pulse. pic18fxx8 ds41159e-page 158 ? 2006 microchip technology inc. figure 17-8: i 2 c? slave mode timing with sen = 0 (reception, 7-bit address) sda scl sspif bf (sspstat<0>) sspov (sspcon1<6>) s 1234 5 67 89 1 23 4567 89 1 2345 7 89 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 (pir1<3>) ckp (ckp does not reset to ? 0 ? when sen = 0 ) ? 2006 microchip technology inc. ds41159e-page 159 pic18fxx8 figure 17-9: i 2 c? slave mode timing (transmission, 7-bit address) sda scl sspif (pir1<3>) bf (sspstat<0>) a6 a5 a4 a3 a2 a1 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 sspbuf is written in software cleared in software from sspif isr data in sampled s ack transmitting data r/w = 1 ack receiving address a7 d7 9 1 d6 d5 d4 d3 d2 d1 d0 2 3 4 5 6 7 8 9 sspbuf is written in software cleared in software from sspif isr transmitting data d7 1 ckp p ack ckp is set in software ckp is set in software scl held low while cpu responds to sspif pic18fxx8 ds41159e-page 160 ? 2006 microchip technology inc. figure 17-10: i 2 c? slave mode timing with sen = 0 (reception, 10-bit address) sda scl sspif bf (sspstat<0>) s 123456 789 123456789 12345 789 p 1 1 1 1 0 a9a8 a7 a6 a5a4a3a2a1 a0 d7 d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 (pir1<3>) cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp 123 45 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon1<6>) sspov is set because sspbuf is still full. ack is not sent. (ckp does not reset to ? 0 ? when sen = 0 ) clock is held low until update of sspadd has taken place ? 2006 microchip technology inc. ds41159e-page 161 pic18fxx8 figure 17-11: i 2 c? slave mode timing (transmission, 10-bit address) sda scl sspif bf (sspstat<0>) s 1234 56 789 123 45 6789 123 45 789 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 1 1 1 1 0 a8 r/w = 1 ack ack r/w = 0 ack receive first byte of address cleared in software bus master terminates transfer a9 6 (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag receive first byte of address 12345 78 9 d7 d6 d5 d4 d3 d1 ack d2 6 transmitting data byte d0 dummy read of sspbuf to clear bf flag sr cleared in software write of sspbuf initiates transmit cleared in software completion of clears bf flag ckp (sspcon1<4>) ckp is set in software ckp is automatically cleared in hardware holding scl low clock is held low until update of sspadd has taken place data transmission clock is held low until ckp is set to ? 1 ? bf flag is clear third address sequence at the end of the pic18fxx8 ds41159e-page 162 ? 2006 microchip technology inc. 17.4.4 clock stretching both 7 and 10-bit slave modes implement automatic clock stretching during a transmit sequence. the sen bit (sspcon2<0>) allows clock stretching to be enabled during receives. setting sen will cause the scl pin to be held low at the end of each data receive sequence. 17.4.4.1 clock stretching for 7-bit slave receive mode (sen = 1 ) in 7-bit slave receive mode, on the falling edge of the ninth clock at the end of the ack sequence, if the bf bit is set, the ckp bit in the sspcon1 register is auto- matically cleared, forcing the scl output to be held low. the ckp being cleared to ? 0 ? will assert the scl line low. the ckp bit must be set in the user?s isr before reception is allowed to continue. by holding the scl line low, the user has time to service the isr and read the contents of the sspbuf before the master device can initiate another receive sequence. this will prevent buffer overruns from occurring. 17.4.4.2 clock stretching for 10-bit slave receive mode (sen = 1 ) in 10-bit slave receive mode, during the address sequence, clock stretching automatically takes place but ckp is not cleared. during this time, if the ua bit is set after the ninth clock, clock stretching is initiated. the ua bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the r/w bit cleared to ? 0 ?. the release of the clock line occurs upon updating sspadd. clock stretching will occur on each data receive sequence as described in 7-bit mode. 17.4.4.3 clock stretching for 7-bit slave transmit mode 7-bit slave transmit mode implements clock stretching by clearing the ckp bit after the falling edge of the ninth clock if the bf bit is clear. this occurs regardless of the state of the sen bit. the user?s isr must set the ckp bit before transmis- sion is allowed to continue. by holding the scl line low, the user has time to service the isr and load the contents of the sspbuf before the master device can initiate another transmit sequence (see figure 17-9). 17.4.4.4 clock stretching for 10-bit slave transmit mode in 10-bit slave transmit mode, clock stretching is controlled during the first two address sequences by the state of the ua bit, just as it is in 10-bit slave receive mode. the first two addresses are followed by a third address sequence which contains the high- order bits of the 10-bit address and the r/w bit set to ? 1 ?. after the third address sequence is performed, the ua bit is not set, the module is now configured in transmit mode and clock stretching is controlled by the bf flag as in 7-bit slave transmit mode (see figure 17-11). note 1: if the user reads the contents of the sspbuf before the falling edge of the ninth clock, thus clearing the bf bit, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit. the user should be careful to clear the bf bit in the isr before the next receive sequence in order to prevent an overflow condition. note: if the user polls the ua bit and clears it by updating the sspadd register before the falling edge of the ninth clock occurs and if the user hasn?t cleared the bf bit by read- ing the sspbuf register before that time, then the ckp bit will still not be asserted low. clock stretching on the basis of the state of the bf bit only occurs during a data sequence, not an address sequence. note 1: if the user loads the contents of sspbuf, setting the bf bit before the falling edge of the ninth clock, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit. ? 2006 microchip technology inc. ds41159e-page 163 pic18fxx8 17.4.4.5 clock synchronization and the ckp bit if a user clears the ckp bit, the scl output is forced to ? 0 ?. setting the ckp bit will not assert the scl output low until the scl output is already sampled low. if the user attempts to drive scl low, the ckp bit will not assert the scl line until an external i 2 c master device has already asserted the scl line. the scl output will remain low until the ckp bit is set and all other devices on the i 2 c bus have deasserted scl. this ensures that a write to the ckp bit will not violate the minimum high time requirement for scl (see figure 17-12). figure 17-12: clock synchronization timing sda scl dx ? 1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspcon1 ckp master device deasserts clock master device asserts clock pic18fxx8 ds41159e-page 164 ? 2006 microchip technology inc. figure 17-13: i 2 c? slave mode timing with sen = 1 (reception, 7-bit address) sda scl sspif bf (sspstat<0>) sspov (sspcon1<6>) s 1 234 56 7 8 9 1 2345 67 89 1 23 45 7 89 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 (pir1<3>) ckp ckp written to ? 1 ? in if bf is cleared prior to the falling edge of the 9th clock, ckp will not be reset to ? 0 ? and no clock stretching will occur software clock is held low until ckp is set to ? 1 ? clock is not held low because buffer full bit is clear prior to falling edge of 9th clock clock is not held low because ack = 1 bf is set after falling edge of the 9th clock, ckp is reset to ? 0 ? and clock stretching occurs ? 2006 microchip technology inc. ds41159e-page 165 pic18fxx8 figure 17-14: i 2 c? slave mode timing with sen = 1 (reception, 10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 56 7 89 1 2345 67 89 1 2345 7 89 p 1 1 1 1 0 a9a8 a7 a6 a5 a4a3a2a1 a0 d7d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 (pir1<3>) cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address after falling edge ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address after falling edge sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon1<6>) ckp written to ? 1 ? note: an update of the sspadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. note: an update of the sspadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. in software clock is held low until update of sspadd has taken place of ninth clock of ninth clock sspov is set because sspbuf is still full. ack is not sent. dummy read of sspbuf to clear bf flag clock is held low until ckp is set to ? 1 ? clock is not held low because ack = 1 pic18fxx8 ds41159e-page 166 ? 2006 microchip technology inc. 17.4.5 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually determines which device will be the slave addressed by the master. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all ? 0 ?s with r/w = 0 . the general call address is recognized when the gen- eral call enable bit (gcen) is enabled (sspcon2<7> set). following a start bit detect, 8 bits are shifted into the sspsr and the address is compared against the sspadd. it is also compared to the general call address and fixed in hardware. if the general call address matches, the sspsr is transferred to the sspbuf, the bf flag bit is set (eighth bit) and on the falling edge of the ninth bit (ack bit), the sspif interrupt flag bit is set. when the interrupt is serviced, the source for the inter- rupt can be checked by reading the contents of the sspbuf. the value can be used to determine if the address was device specific or a general call address. in 10-bit mode, the sspadd is required to be updated for the second half of the address to match and the ua bit is set (sspstat<1>). if the general call address is sampled when the gcen bit is set, while the slave is configured in 10-bit address mode, then the second half of the address is not necessary, the ua bit will not be set and the slave will begin receiving data after the acknowledge (figure 17-15). figure 17-15: slave mode general call address sequence (7 or 10-bit address mode) sda scl s sspif bf (sspstat<0>) sspov (sspcon1<6>) cleared in software sspbuf is read r/w = 0 ack general call address address is compared to general call address gcen (sspcon2<7>) receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack, set interrupt ? 0 ? ? 1 ? ? 2006 microchip technology inc. ds41159e-page 167 pic18fxx8 17.4.6 master mode master mode is enabled by setting and clearing the appropriate sspm bits in sspcon1 and by setting the sspen bit. in master mode, the scl and sda lines are manipulated by the mssp hardware. master mode of operation is supported by interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit is set or the bus is idle, with both the s and p bits clear. in firmware controlled master mode, user code conducts all i 2 c bus operations based on start and stop bit conditions. once master mode is enabled, the user has six options. 1. assert a start condition on sda and scl. 2. assert a repeated start condition on sda and scl. 3. write to the sspbuf register initiating transmission of data/address. 4. configure the i 2 c port to receive data. 5. generate an acknowledge condition at the end of a received byte of data. 6. generate a stop condition on sda and scl. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt if enabled): ? start condition ? stop condition ? data transfer byte transmitted/received ? acknowledge transmit ? repeated start figure 17-16: mssp block diagram (i 2 c? master mode) note: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspbuf register to initiate transmission before the start condition is complete. in this case, the sspbuf will not be written to and the wcol bit will be set, indicating that a write to the sspbuf did not occur. read write sspsr start bit, stop bit, sspbuf internal data bus set/reset s, p, wcol (sspstat); shift clock msb lsb sda acknowledge generate scl scl in bus collision sda in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspadd<6:0> baud set sspif, bclif; reset ackstat, pen (sspcon2) rate generator sspm3:sspm0 start bit detect stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv pic18fxx8 ds41159e-page 168 ? 2006 microchip technology inc. 17.4.6.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition, or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic ? 0 ?. serial data is transmitted 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted con- tains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic ? 1 ?. thus, the first byte transmitted is a 7-bit slave address followed by a ? 1 ? to indicate receive bit. serial data is received via sda while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions indicate the beginning and end of transmission. the baud rate generator used for the spi mode operation is used to set the scl clock frequency for either 100 khz, 400 khz or 1 mhz i 2 c operation. see section 17.4.7 ?baud rate generator? for more details. a typical transmit sequence would go as follows: 1. the user generates a start condition by setting the start enable bit, sen (sspcon2<0>). 2. sspif is set. the mssp module will wait the required start time before any other operation takes place. 3. the user loads the sspbuf with the slave address to transmit. 4. address is shifted out the sda pin until all 8 bits are transmitted. 5. the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). 6. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 7. the user loads the sspbuf with eight bits of data. 8. data is shifted out the sda pin until all 8 bits are transmitted. 9. the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). 10. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 11. the user generates a stop condition by setting the stop enable bit pen (sspcon2<2>). 12. interrupt is generated once the stop condition is complete. ? 2006 microchip technology inc. ds41159e-page 169 pic18fxx8 17.4.7 baud rate generator in i 2 c master mode, the baud rate generator (brg) reload value is placed in the lower 7 bits of the sspadd register (figure 17-17). when a write occurs to sspbuf, the baud rate generator will automatically begin counting. the brg counts down to 0 and stops until another reload has taken place. the brg count is decremented twice per instruction cycle (t cy ) on the q2 and q4 clocks. in i 2 c master mode, the brg is reloaded automatically. once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ack ), the internal clock will automatically stop counting and the scl pin will remain in its last state. table 17-3 demonstrates clock rates based on instruction cycles and the brg value loaded into sspadd. figure 17-17: baud rate generator block diagram table 17-3: i 2 c? clock rate w/brg sspm3:sspm0 brg down counter clko f osc /4 sspadd<6:0> sspm3:sspm0 scl reload control reload f osc f cy f cy * 2 brg value f scl (2 rollovers of brg) 40 mhz 10 mhz 20 mhz 18h 400 khz (1) 40 mhz 10 mhz 20 mhz 1fh 312.5 khz 40 mhz 10 mhz 20 mhz 63h 100 khz 16 mhz 4 mhz 8 mhz 09h 400 khz (1) 16 mhz 4 mhz 8 mhz 0ch 308 khz 16 mhz 4 mhz 8 mhz 27h 100 khz 4 mhz 1 mhz 2 mhz 02h 333 khz (1) 4 mhz 1 mhz 2 mhz 09h 100khz 4 mhz 1 mhz 2 mhz 00h 1 mhz (1) note 1: the i 2 c? interface does not conform to the 400 khz i 2 c specification (which applies to rates greater than 100 khz) in all details, but may be used with care where higher rates are required by the application. pic18fxx8 ds41159e-page 170 ? 2006 microchip technology inc. 17.4.7.1 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, deasserts the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device (figure 17-18). figure 17-18: baud rate generator timing with clock arbitration sda scl scl deasserted but slave holds dx ? 1 dx brg scl is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements on q2 and q4 cycles ? 2006 microchip technology inc. ds41159e-page 171 pic18fxx8 17.4.8 i 2 c master mode start condition timing to initiate a start condition, the user sets the start condition enable bit, sen (sspcon2<0>). if the sda and scl pins are sampled high, the baud rate gener- ator is reloaded with the contents of sspadd<6:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low, while scl is high, is the start condition and causes the s bit (sspstat<3>) to be set. following this, the baud rate generator is reloaded with the contents of sspadd<6:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit (sspcon2<0>) will be automatically cleared by hardware, the baud rate generator is suspended, leaving the sda line held low and the start condition is complete. 17.4.8.1 wcol status flag if the user writes the sspbuf when a start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 17-19: first start bit timing note: if, at the beginning of the start condition, the sda and scl pins are already sam- pled low, or if during the start condition, the scl line is sampled low before the sda line is driven low, a bus collision occurs; the bus collision interrupt flag, bclif, is set, the start condition is aborted and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete. sda scl s t brg 1st bit 2nd bit t brg sda = 1 , at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspstat<3>) and sets sspif bit pic18fxx8 ds41159e-page 172 ? 2006 microchip technology inc. 17.4.9 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit (sspcon2<1>) is programmed high and the i 2 c logic module is in the idle state. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sam- pled low, the baud rate generator is loaded with the contents of sspadd<5:0> and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate genera- tor times out, if sda is sampled high, the scl pin will be deasserted (brought high). when scl is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda = 0 ) for one t brg while scl is high. following this, the rsen bit (sspcon2<1>) will be automatically cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit (sspstat<3>) will be set. the sspif bit will not be set until the baud rate generator has timed out. immediately following the sspif bit getting set, the user may write the sspbuf with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. after the first eight bits are transmitted and an ack is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 17.4.9.1 wcol status flag if the user writes the sspbuf when a repeated start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 17-20: repeated start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: ? sda is sampled low when scl goes from low-to-high. ? scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data ? 1 ?. note: because queueing of events is not allowed, writing of the lower 5 bits of sspcon2 is disabled until the repeated start condition is complete. sda scl sr = repeated start write to sspcon2 write to sspbuf occurs here falling edge of ninth clock end of xmit at completion of start bit, hardware clears rsen bit 1st bit set s (sspstat<3>) t brg t brg sda = 1 , sda = 1 , scl (no change). scl = 1 occurs here. t brg t brg t brg and sets sspif ? 2006 microchip technology inc. ds41159e-page 173 pic18fxx8 17.4.10 i 2 c master mode transmission transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the sspbuf register. this action will set the buffer full flag bit bf and allow the baud rate generator to begin counting and start the next trans- mission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted (see data hold time specification parameter #106). scl is held low for one baud rate generator rollover count (t brg ). data should be valid before scl is released high (see data setup time specification parameter #107). when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sda. this allows the slave device being addressed to respond with an ack bit during the ninth bit time, if an address match occurred, or if data was received prop- erly. the status of ack is written into the ackdt bit on the falling edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared. if not, the bit is set. after the ninth clock, the sspif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspbuf, leaving scl low and sda unchanged (figure 17-21). after the write to the sspbuf, each bit of address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the falling edge of the eighth clock, the master will deassert the sda pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit (sspcon2<6>). following the falling edge of the ninth clock transmis- sion of the address, the sspif bit is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspbuf takes place, holding scl low and allowing sda to float. 17.4.10.1 bf status flag in transmit mode, the bf bit (sspstat<0>) is set when the cpu writes to sspbuf and is cleared when all 8 bits are shifted out. 17.4.10.2 wcol status flag if the user writes the sspbuf when a transmit is already in progress (i.e., sspsr is still shifting out a data byte), the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). wcol must be cleared in software. 17.4.10.3 ackstat status flag in transmit mode, the ackstat bit (sspcon2<6>) is cleared when the slave has sent an acknowledge (ack = 0 ) and is set when the slave does not acknowl- edge (ack = 1 ). a slave sends an acknowledge when it has recognized its address (including a general call) or when the slave has properly received its data. 17.4.11 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen (sspcon2<3>). the baud rate generator begins counting and on each rollover, the state of the scl pin changes (high-to-low/ low-to-high) and data is shifted into the sspsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the sspsr are loaded into the sspbuf, the bf flag bit is set, the sspif flag bit is set and the baud rate gener- ator is suspended from counting, holding scl low. the mssp is now in idle state awaiting the next command. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception by setting the acknowledge sequence enable bit, acken (sspcon2<4>). 17.4.11.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when the sspbuf register is read. 17.4.11.2 sspov status flag in receive operation, the sspov bit is set when 8 bits are received into the sspsr and the bf flag bit is already set from a previous reception. 17.4.11.3 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e., sspsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write doesn?t occur). note: the rcen bit should be set after the ack sequence is complete or the rcen bit will be disregarded. pic18fxx8 ds41159e-page 174 ? 2006 microchip technology inc. figure 17-21: i 2 c? master mode waveform (transmission, 7 or 10-bit address) sda scl sspif bf (sspstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspbuf is written in software from ssp interrupt after start condition, sen cleared by hardware s sspbuf written with 7-bit address and r/w , start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> sen = 1 start condition begins from slave, clear ackstat bit sspcon2<6> ackstat in sspcon2 = 1 cleared in software sspbuf written pen r/w cleared in software ? 2006 microchip technology inc. ds41159e-page 175 pic18fxx8 figure 17-22: i 2 c? master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 1 transmit address to slave sspif bf ack is not sent write to sspcon2<0> (sen = 1 ), write to sspbuf occurs here, ack from slave master configured as a receiver by programming sspcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit sen = 0 sspov sda = 0 , scl = 1 while cpu (sspstat<0>) ack cleared in software cleared in software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif ack from master set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of receive set acken, start acknowledge sequence sda = ackdt = 1 rcen cleared automatically rcen = 1, start next receive write to sspcon2<4> to start acknowledge sequence sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspif acken begin start condition cleared in software sda = ackdt = 0 cleared in software sspov is set because sspbuf is still full last bit is shifted into sspsr and contents are unloaded into sspbuf pic18fxx8 ds41159e-page 176 ? 2006 microchip technology inc. 17.4.12 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken (sspcon2<4>). when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit are presented on the sda pin. if the user wishes to gen- erate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the scl pin is deasserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is automatically cleared, the baud rate generator is turned off and the mssp module then goes into idle mode (figure 17-23). 17.4.12.1 wcol status flag if the user writes the sspbuf when an acknowledge sequence is in progress, then wcol is set and the con- tents of the buffer are unchanged (the write doesn?t occur). 17.4.13 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen (sspcon2<2>). at the end of a receive/ transmit, the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sampled low, the baud rate generator is reloaded and counts down to 0. when the baud rate generator times out, the scl pin will be brought high and one t brg (baud rate generator rollover count) later, the sda pin will be deasserted. when the sda pin is sampled high while scl is high, the p bit (sspstat<4>) is set. a t brg later, the pen bit is cleared and the sspif bit is set (figure 17-24). 17.4.13.1 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then the wcol bit is set and the con- tents of the buffer are unchanged (the write doesn?t occur). figure 17-23: acknowledge sequence waveform figure 17-24: stop cond ition receive or transmit mode note: t brg = one baud rate generator period. sda scl set sspif at the end acknowledge sequence starts here, write to sspcon2 acken automatically cleared cleared in t brg t brg of receive 8 acken = 1 , ackdt = 0 d0 9 sspif software set sspif at the end of acknowledge sequence cleared in software ack scl sda sda asserted low before rising edge of clock write to sspcon2 set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspstat<4>) is set. t brg to setup stop condition ack p t brg pen bit (sspcon2<2>) is cleared by hardware and the sspif bit is set ? 2006 microchip technology inc. ds41159e-page 177 pic18fxx8 17.4.14 sleep operation while in sleep mode, the i 2 c module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp interrupt is enabled). 17.4.15 effect of a reset a reset disables the mssp module and terminates the current transfer. 17.4.16 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit (sspstat<4>) is set, or the bus is idle, with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored for arbitration to see if the signal level is the expected output level. this check is performed in hardware with the result placed in the bclif bit. the states where arbitration can be lost are: ? address transfer ? data transfer ? a start condition ? a repeated start condition ? an acknowledge condition 17.4.17 multi -master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a ? 1 ? on sda by letting sda float high and another master asserts a ? 0 ?. when the scl pin floats high, data should be stable. if the expected data on sda is a ? 1 ? and the data sampled on the sda pin = 0 , then a bus collision has taken place. the master will set the bus collision interrupt flag bclif and reset the i 2 c port to its idle state (figure 17-25). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are deasserted and the sspbuf can be written to. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are deasserted and the respective control bits in the sspcon2 register are cleared. when the user ser- vices the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins. if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the determi- nation of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat register or the bus is idle and the s and p bits are cleared. figure 17-25: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high, data doesn?t match what is driven bus collision has occurred. set bus collision interrupt (bclif) by the master. by master data changes while scl = 0 pic18fxx8 ds41159e-page 178 ? 2006 microchip technology inc. 17.4.17.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition (figure 17-26). b) scl is sampled low before sda is asserted low (figure 17-27). during a start condition, both the sda and the scl pins are monitored. if the sda pin is already low, or the scl pin is already low, then all of the following occur: ? the start condition is aborted, ? the bclif flag is set and ? the mssp module is reset to its idle state (figure 17-26). the start condition begins with the sda and scl pins deasserted. when the sda pin is sampled high, the baud rate generator is loaded from sspadd<6:0> and counts down to 0. if the scl pin is sampled low while sda is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ? 1 ? during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early (figure 17-28). if, however, a ? 1 ? is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to 0 and during this time, if the scl pins are sampled as ? 0 ?, a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 17-26: bus collision during start condition (sda only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus colli- sion because the two masters must be allowed to arbitrate the first address following the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1 , scl = 1 sda = 0 , scl = 1 . bclif s sspif sda = 0 , scl = 1 . sspif and bclif are cleared in software sspif and bclif are cleared in software. set bclif, start condition. set bclif. ? 2006 microchip technology inc. ds41159e-page 179 pic18fxx8 figure 17-27: bus collision d uring start condition (scl = 0 ) figure 17-28: brg reset due to sda arbitrat ion during start condition sda scl sen bus collision occurs. set bclif. scl = 0 before sda = 0 , set sen, enable start sequence if sda = 1 , scl = 1 t brg t brg sda = 0 , scl = 1 bclif s sspif interrupt cleared in software bus collision occurs. set bclif. scl = 0 before brg time-out, ? 0 ?? 0 ? ? 0 ? ? 0 ? sda scl sen set s less than t brg t brg sda = 0 , scl = 1 bclif s sspif s interrupts cleared in software set sspif sda = 0 , scl = 1 , scl pulled low after brg time-out set sspif ? 0 ? sda pulled low by other master. reset brg and assert sda. set sen, enable start sequence if sda = 1 , scl = 1 pic18fxx8 ds41159e-page 180 ? 2006 microchip technology inc. 17.4.17.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indicating that another master is attempting to transmit a data ? 1 ?. when the user deasserts sda and the pin is allowed to float high, the brg is loaded with sspadd<6:0> and counts down to 0. the scl pin is then deasserted and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ? 0 ?, figure 17-29). if sda is sampled high, the brg is reloaded and begins counting. if sda goes from high-to-low before the brg times out, no bus collision occurs because no two masters can assert sda at exactly the same time. if scl goes from high-to-low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ? 1 ? during the repeated start condition (figure 17-30). if, at the end of the brg time-out, both scl and sda are still high, the sda pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 17-29: bus collision during a repeat ed start condition (case 1) figure 17-30: bus collision during a repe ated start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0 , set bclif and release sda and scl. cleared in software ? 0 ? ? 0 ? sda scl bclif rsen s sspif interrupt cleared in software scl goes low before sda, set bclif. release sda and scl. t brg t brg ? 0 ? ? 2006 microchip technology inc. ds41159e-page 181 pic18fxx8 17.4.17.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been deasserted and allowed to float high, sda is sampled low after the brg has timed out. b) after the scl pin is deasserted, scl is sampled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd<6:0> and counts down to 0. after the brg times out, sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data ? 0 ? (figure 17-31). if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data ? 0 ? (figure 17-32). figure 17-31: bus collision during a stop condition (case 1) figure 17-32: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif ? 0 ? ? 0 ? sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high, set bclif ? 0 ? ? 0 ? pic18fxx8 ds41159e-page 182 ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. ds41159e-page 183 pic18fxx8 18.0 addressable universal synchronous asynchronous receiver transmitter (usart) the universal synchronous asynchronous receiver transmitter (usart) module is one of the three serial i/o modules incorporated into pic18fxx8 devices. (usart is also known as a serial communications interface or sci.) the usart can be configured as a full-duplex asynchronous system that can communi- cate with peripheral devices, such as crt terminals and personal computers, or it can be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms, etc. the usart can be configured in the following modes: ? asynchronous (full-duplex) ? synchronous ? master (half-duplex) ? synchronous ? slave (half-duplex). the spen (rcsta register) and the trisc<7> bits have to be set and the trisc<6> bit must be cleared in order to configure pins rc6/tx/ck and rc7/rx/dt as the universal synchronous asynchronous receiver transmitter. register 18-1 shows the transmit status and control register (txsta) and register 18-2 shows the receive status and control register (rcsta). register 18-1: txsta: transmit status and control register r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync ?brghtrmttx9d bit 7 bit 0 bit 7 csrc: clock source select bit asynchronous mode: don?t care. synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9 : 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode. bit 4 sync: usart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 unimplemented: read as ? 0 ? bit 2 brgh : high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode. bit 1 trmt : transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data can be address/data bit or a parity bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 184 ? 2006 microchip technology inc. register 18-2: rcsta: receive status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 bit 7 spen: serial port enable bit 1 = serial port enabled (configures rx/dt and tx/ck pins as serial port pins) 0 = serial port disabled bit 6 rx9 : 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren : single receive enable bit asynchronous mode: don?t care. synchronous mode ? master: 1 = enables single receive 0 = disables single receive (this bit is cleared after reception is complete) synchronous mode ? slave: unused in this mode. bit 4 cren : continuous receive enable bit asynchronous mode: 1 = enables continuous receive 0 = disables continuous receive synchronous mode: 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden : address detect enable bit asynchronous mode 9-bit (rx9 = 1 ): 1 = enables address detection, enables interrupt and load of the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit bit 2 ferr : framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1 oerr : overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data can be address/data bit or a parity bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 185 pic18fxx8 18.1 usart baud rate generator (brg) the brg supports both the asynchronous and synchronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free running, 8-bit timer. in asynchronous mode, bit brgh (txsta register) also controls the baud rate. in synchronous mode, bit brgh is ignored. table 18-1 shows the formula for computation of the baud rate for different usart modes which only apply in master mode (internal clock). given the desired baud rate and f osc , the nearest integer value for the spbrg register can be calculated using the formula in table 18-1. from this, the error in baud rate can be determined. example 18-1 shows the calculation of the baud rate error for the following conditions: f osc = 16 mhz desired baud rate = 9600 brgh = 0 sync = 0 it may be advantageous to use the high baud rate (brgh = 1 ) even for slower baud clocks. this is because the f osc /(16(x + 1)) equation can reduce the baud rate error in some cases. writing a new value to the spbrg register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before outputting the new baud rate. 18.1.1 sampling the data on the rc7/rx/dt pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx pin. example 18-1: calculating baud rate error table 18-1: baud rate formula table 18-2: registers associated with baud rate generator desired baud rate = f osc /(64 (x + 1)) solving for x: x = ((f osc /desired baud rate)/64) ? 1 x = ((16000000/9600)/64) ? 1 x = [25.042] = 25 calculated baud rate = 16000000/(64 (25 + 1)) = 9615 error = (calculated baud rate ? desired baud rate) desired baud rate = (9615 ? 9600)/9600 =0.16% sync brgh = 0 (low speed) brgh = 1 (high speed) 0 1 (asynchronous) baud rate = f osc /(64 (x + 1)) (synchronous) baud rate = f osc /(4 (x + 1)) baud rate = f osc /(16 (x + 1)) na legend: x = value in spbrg (0 to 255) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000u spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used by the brg. pic18fxx8 ds41159e-page 186 ? 2006 microchip technology inc. table 18-3: baud rates for synchronous mode baud rate (kbps) f osc = 40 mhz spbrg value (decimal) 33 mhz spbrg value (decimal) 25 mhz spbrg value (decimal) 20 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 na - - na - - na - - na - - 1.2 na - - na - - na - - na - - 2.4 na - - na - - na - - na - - 9.6 na - - na - - na - - na - - 19.2 na - - na - - na - - na - - 76.8 76.92 +0.16 129 77.10 +0.39 106 77.16 +0.47 80 76.92 +0.16 64 96 96.15 +0.16 103 95.93 -0.07 85 96.15 +0.16 64 96.15 +0.16 51 300 303.03 +1.01 32 294.64 -1.79 27 297.62 -0.79 20 294.12 -1.96 16 500 500 0 19 485.30 -2.94 16 480.77 -3.85 12 500 0 9 high 10000 - 0 8250 - 0 6250 - 0 5000 - 0 low 39.06 - 255 32.23 - 255 24.41 - 255 19.53 - 255 baud rate (kbps) f osc = 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.15909 mhz spbrg value (decimal) 5.0688 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3na- - na- - na - - na- - 1.2na- - na- - na - - na- - 2.4na- - na- - na - - na- - 9.6 na - - na - - 9.62 +0.23 185 9.60 0 131 19.2 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92 19.20 0 65 76.8 76.92 +0.16 51 75.76 -1.36 32 77.82 +1.32 22 74.54 -2.94 16 96 95.24 -0.79 41 96.15 +0.16 25 94.20 -1.88 18 97.48 +1.54 12 300 307.70 +2.56 12 312.50 +4.17 7 298.35 -0.57 5 316.80 +5.60 3 500 500 0 7 500 0 4 447.44 -10.51 3 422.40 -15.52 2 high 4000 - 0 2500 - 0 1789.80 - 0 1267.20 - 0 low 15.63 - 255 9.77 - 255 6.99 - 255 4.95 - 255 baud rate (kbps) f osc = 4 mhz spbrg value (decimal) 3.579545 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 na - - na - - na - - 0.30 +1.14 26 1.2 na - - na - - 1.20 +0.16 207 1.17 -2.48 6 2.4 na - - na - - 2.40 +0.16 103 2.73 +13.78 2 9.6 9.62 +0.16 103 9.62 +0.23 92 9.62 +0.16 25 8.20 -14.67 0 19.2 19.23 +0.16 51 19.04 -0.83 46 19.23 +0.16 12 na - - 76.8 76.92 +0.16 12 74.57 -2.90 11 83.33 +8.51 2 na - - 96 1000 +4.17 9 99.43 +3.57 8 83.33 -13.19 2 na - - 300 333.33 +11.11 2 298.30 -0.57 2 250 -16.67 0 na - - 500 500 0 1 447.44 -10.51 1 na - - na - - high 1000 - 0 894.89 - 0 250 - 0 8.20 - 0 low 3.91 - 255 3.50 - 255 0.98 - 255 0.03 - 255 ? 2006 microchip technology inc. ds41159e-page 187 pic18fxx8 table 18-4: baud rates for asynchronous mode (brgh = 0 ) baud rate (kbps) f osc = 40 mhz spbrg value (decimal) 33 mhz spbrg value (decimal) 25 mhz spbrg value (decimal) 20 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 na - - na - - na - - na - - 1.2 na - - na - - na - - na - - 2.4 na - - 2.40 -0.07 214 2.40 -0.15 162 2.40 +0.16 129 9.6 9.62 +0.16 64 9.55 -0.54 53 9.53 -0.76 40 9.47 -1.36 32 19.2 18.94 -1.36 32 19.10 -0.54 26 19.53 +1.73 19 19.53 +1.73 15 76.8 78.13 +1.73 7 73.66 -4.09 6 78.13 +1.73 4 78.13 +1.73 3 96 89.29 -6.99 6 103.13 +7.42 4 97.66 +1.73 3 104.17 +8.51 2 300 312.50 +4.17 1 257.81 -14.06 1 na - - 312.50 +4.17 0 500 625 +25.00 0 na - - na - - na - - high 625 - 0 515.63 - 0 390.63 - 0 312.50 - 0 low 2.44 - 255 2.01 - 255 1.53 - 255 1.22 - 255 baud rate (kbps) f osc = 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.15909 mhz spbrg value (decimal) 5.0688 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 na - - na - - na - - na - - 1.2 1.20 +0.16 207 1.20 +0.16 129 1.20 +0.23 92 1.20 0 65 2.4 2.40 +0.16 103 2.40 +0.16 64 2.38 -0.83 46 2.40 0 32 9.6 9.62 +0.16 25 9.77 +1.73 15 9.32 -2.90 11 9.90 +3.13 7 19.2 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5 19.80 +3.13 3 76.8 83.33 +8.51 2 78.13 +1.73 1 111.86 +45.65 0 79.20 +3.13 0 96 83.33 -13.19 2 78.13 -18.62 1 na - - na - - 300 250 -16.67 0 156.25 -47.92 0 na - - na - - 500 na - - na - - na - - na - - high 250 - 0 156.25 - 0 111.86 - 0 79.20 - 0 low 0.98 - 255 0.61 - 255 0.44 - 255 0.31 - 255 baud rate (kbps) f osc = 4 mhz spbrg value (decimal) 3.579545 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 0.30 -0.16 207 0.30 +0.23 185 0.30 +0.16 51 0.26 -14.67 1 1.2 1.20 +1.67 51 1.19 -0.83 46 1.20 +0.16 12 na - - 2.4 2.40 +1.67 25 2.43 +1.32 22 2.23 -6.99 6 na - - 9.6 8.93 -6.99 6 9.32 -2.90 5 7.81 -18.62 1 na - - 19.2 20.83 +8.51 2 18.64 -2.90 2 15.63 -18.62 0 na - - 76.8 62.50 -18.62 0 55.93 -27.17 0 na - - na - - 96 na - - na - - na - - na - - 300 na - - na - - na - - na - - 500 na - - na - - na - - na - - high 62.50 - 0 55.93 - 0 15.63 - 0 0.51 - 0 low 0.24 - 255 0.22 - 255 0.06 - 255 0.002 - 255 pic18fxx8 ds41159e-page 188 ? 2006 microchip technology inc. table 18-5: baud rates for asynchronous mode (brgh = 1 ) baud rate (kbps) f osc = 40 mhz spbrg value (decimal) 33 mhz spbrg value (decimal) 25 mhz spbrg value (decimal) 20 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3na- -na- -na- -na- - 1.2na- -na- -na- -na- - 2.4na- -na- -na- -na- - 9.6 na - - 9.60 -0.07 214 9.59 -0.15 162 9.62 +0.16 129 19.2 19.23 +0.16 129 19.28 +0.39 106 19.30 +0.47 80 19.23 +0.16 64 76.8 75.76 -1.36 32 76.39 -0.54 26 78.13 +1.73 19 78.13 +1.73 15 96 96.15 +0.16 25 98.21 +2.31 20 97.66 +1.73 15 96.15 +0.16 12 300 312.50 +4.17 7 294.64 -1.79 6 312.50 +4.17 4 312.50 +4.17 3 500 500 0 4 515.63 +3.13 3 520.83 +4.17 2 416.67 -16.67 2 high 2500 - 0 2062.50 - 0 1562.50 - 0 1250 - 0 low 9.77 - 255 8,06 - 255 6.10 - 255 4.88 - 255 baud rate (kbps) f osc = 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.15909 mhz spbrg value (decimal) 5.0688 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3na- - na- - na- - na- - 1.2na- - na- - na- - na- - 2.4 na - - na - - 2.41 +0.23 185 2.40 0 131 9.6 9.62 +0.16 103 9.62 +0.16 64 9.52 -0.83 46 9.60 0 32 19.2 19.23 +0.16 51 18.94 -1.36 32 19.45 +1.32 22 18.64 -2.94 16 76.8 76.92 +0.16 12 78.13 +1.73 7 74.57 -2.90 5 79.20 +3.13 3 96 100 +4.17 9 89.29 -6.99 6 89.49 -6.78 4 105.60 +10.00 2 300 333.33 +11.11 2 312.50 +4.17 1 447.44 +49.15 0 316.80 +5.60 0 500 500 0 1 625 +25.00 0 447.44 -10.51 0 na - - high 1000 - 0 625 - 0 447.44 - 0 316.80 - 0 low 3.91 - 255 2.44 - 255 1.75 - 255 1.24 - 255 baud rate (kbps) f osc = 4 mhz spbrg value (decimal) 3.579545 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 na - - na - - 0.30 +0.16 207 0.29 -2.48 6 1.2 1.20 +0.16 207 1.20 +0.23 185 1.20 +0.16 51 1.02 -14.67 1 2.4 2.40 +0.16 103 2.41 +0.23 92 2.40 +0.16 25 2.05 -14.67 0 9.6 9.62 +0.16 25 9.73 +1.32 22 8.93 -6.99 6 na - - 19.2 19.23 +0.16 12 18.64 -2.90 11 20.83 +8.51 2 na - - 76.8 na - - 74.57 -2.90 2 62.50 -18.62 0 na - - 96 na - - 111.86 +16.52 1 na - - na - - 300 na - - 223.72 -25.43 0 na - - na - - 500na- - na- - na- - na- - high 250 - 0 55.93 - 0 62.50 - 0 2.05 - 0 low 0.98 - 255 0.22 - 255 0.24 - 255 0.008 - 255 ? 2006 microchip technology inc. ds41159e-page 189 pic18fxx8 18.2 usart asynchronous mode in this mode, the usart uses standard non-return- to-zero (nrz) format (one start bit, eight or nine data bits and one stop bit). the most common data format is 8 bits. an on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the usart transmits and receives the lsb first. the usart?s transmitter and receiver are functionally independent but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on the brgh bit (txsta regis- ter). parity is not supported by the hardware but can be implemented in software (and stored as the ninth data bit). asynchronous mode is stopped during sleep. asynchronous mode is selected by clearing the sync bit (txsta register). the usart asynchronous module consists of the following important elements: ? baud rate generator ? sampling circuit ? asynchronous transmitter ? asynchronous receiver. 18.2.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 18-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the tsr register obtains its data from the read/write transmit buffer register (txreg). the txreg register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg register (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg register is empty and flag bit txif (pir1 register) is set. this interrupt can be enabled/disabled by setting/clearing enable bit txie (pie1 register). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in software. it will reset only when new data is loaded into the txreg register. while flag bit, txif, indicated the status of the txreg register, another bit, trmt (txsta register), shows the status of the tsr register. status bit trmt is a read-only bit which is set when the tsr register is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. steps to follow when setting up an asynchronous transmission: 1. initialize the spbrg register for the appropriate baud rate. if a high-speed baud rate is desired, set bit brgh ( section 18.1 ?usart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set transmit bit tx9. can be used as address/data bit. 5. enable the transmission by setting bit txen which will also set bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts transmission). figure 18-1: usart transmit block diagram note 1: the tsr register is not mapped in data memory, so it is not available to the user. 2: flag bit txif is set when enable bit txen is set. note: txif is not cleared immediately upon loading data into the transmit buffer txreg. the flag bit becomes valid in the second instruction cycle following the load instruction. txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen rc6/tx/ck pin pin buffer and control 8 ? ? ? pic18fxx8 ds41159e-page 190 ? 2006 microchip technology inc. figure 18-2: asynchronous transmission figure 18-3: asynchronous transmission (back to back) table 18-6: registers associated with asynchronous transmission word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg brg output (shift clock) rc6/tx/ck (pin) txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) word 1 transmit shift reg. write to txreg brg output (shift clock) rc6/tx/ck (pin) txif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000u txreg usart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous transmission. note 1: these registers or register bits are not implemented on the pic18f248 and pic18f258 and read as ? 0 ?s. ? 2006 microchip technology inc. ds41159e-page 191 pic18fxx8 18.2.2 usart asynchronous receiver the receiver block diagram is shown in figure 18-4. the data is received on the rc7/rx/dt pin and drives the data recovery block. the data recovery block is actually a high-speed shifter, operating at x16 times the baud rate, whereas the main receive serial shifter oper- ates at the bit rate or at f osc . this mode would typically be used in rs-232 systems. steps to follow when setting up an asynchronous reception: 1. initialize the spbrg register for the appropriate baud rate. if a high-speed baud rate is desired, set bit brgh ( section 18.1 ?usart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit rcie. 4. if 9-bit reception is desired, set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit rcif will be set when reception is complete and an interrupt will be generated if enable bit rcie was set. 7. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg register. 9. if any error occurred, clear the error by clearing enable bit cren. 18.2.3 setting up 9-bit mode with address detect this mode would typically be used in rs-485 systems. steps to follow when setting up an asynchronous reception with address detect enable: 1. initialize the spbrg register for the appropriate baud rate. if a high-speed baud rate is required, set the brgh bit. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are required, set the rcen bit and select the desired priority level with the rcip bit. 4. set the rx9 bit to enable 9-bit reception. 5. set the adden bit to enable address detect. 6. enable reception by setting the cren bit. 7. the rcif bit will be set when reception is complete. the interrupt will be acknowledged if the rcie and gie bits are set. 8. read the rcsta register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. read rcreg to determine if the device is being addressed. 10. if any error occurred, clear the cren bit. 11. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and interrupt the cpu. figure 18-4: usart receive block diagram x64 baud rate clk spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 64 16 or stop start (8) 7 1 0 rx9 ? ? ? note: i/o pins have diode protection to v dd and v ss . pic18fxx8 ds41159e-page 192 ? 2006 microchip technology inc. figure 18-5: asynchronous reception table 18-7: registers associated with asynchronous reception start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx (pin) reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000u rcreg usart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous reception. note 1: these registers or register bi ts are not implemented on the pic18f248 and pic18f258 and read as ? 0 ?s. ? 2006 microchip technology inc. ds41159e-page 193 pic18fxx8 18.3 usart synchronous master mode in synchronous master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit sync (txsta register). in addition, enable bit spen (rcsta register) is set in order to configure the rc6/tx/ck and rc7/rx/dt i/o pins to ck (clock) and dt (data) lines, respectively. the master mode indicates that the processor transmits the master clock on the ck line. the master mode is entered by setting bit csrc (txsta register). 18.3.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 18-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register (txreg). the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg is empty and interrupt bit txif (pir1 register) is set. the interrupt can be enabled/disabled by setting/clearing enable bit txie (pie1 register). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in software. it will reset only when new data is loaded into the txreg register. while flag bit, txif, indicates the status of the txreg register, another bit, trmt (txsta register), shows the status of the tsr register. trmt is a read-only bit which is set when the tsr is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. the tsr is not mapped in data memory, so it is not available to the user. steps to follow when setting up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate ( section 18.1 ?usart baud rate generator (brg)? ). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. table 18-8: registers associated with synchronous master transmission note: txif is not cleared immediately upon loading data into the transmit buffer txreg. the flag bit becomes valid in the second instruction cycle following the load instruction. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000u txreg usart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master transmission. note 1: these registers or register bits are not im plemented on the pic18f248 and pic18f258 and read as ? 0 ?s. pic18fxx8 ds41159e-page 194 ? 2006 microchip technology inc. figure 18-6: synchronous transmission figure 18-7: synchronous transmissi on (through txen) bit 0 bit 1 bit 7 word 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx/dt rc6/tx/ck write to txreg reg txif bit (interrupt flag) trmt txen bit ? 1 ? ? 1 ? note: sync master mode; spbrg = 0 ; continuous transmission of two 8-bit words. word 2 trmt bit write word 1 write word 2 pin pin q3 rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit ? 2006 microchip technology inc. ds41159e-page 195 pic18fxx8 18.3.2 usart synchronous master reception once synchronous master mode is selected, reception is enabled by setting either enable bit sren (rcsta register) or enable bit cren (rcsta register). data is sampled on the rc7/rx/dt pin on the falling edge of the clock. if enable bit sren is set, only a single word is received. if enable bit cren is set, the reception is continuous until cren is cleared. if both bits are set, then cren takes precedence. steps to follow when setting up a synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate ( section 18.1 ?usart baud rate generator (brg)? ). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, set enable bit rcie. 5. if 9-bit reception is desired, set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception, set bit cren. 7. interrupt flag bit rcif will be set when reception is complete and an interrupt will be generated if the enable bit rcie was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing bit cren. table 18-9: registers associated with synchronous master reception figure 18-8: synchronous reception (master mode, sren) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000u rcreg usart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used fo r synchronous master reception. note 1: these registers or register bits are not im plemented on the pic18f248 and pic18f258 and read as ? 0 ?s. cren bit rc7/rx/dt pin rc6/tx/ck pin write to bit sren sren bit rcif bit (interrupt) read rxreg note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 . q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? q1 q2 q3 q4 pic18fxx8 ds41159e-page 196 ? 2006 microchip technology inc. 18.4 usart synchronous slave mode synchronous slave mode differs from the master mode in that the shift clock is supplied externally at the rc6/ tx/ck pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in sleep mode. slave mode is entered by clearing bit csrc (txsta register). 18.4.1 usart synchronous slave transmit the operation of the synchronous master and slave modes are identical, except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in txreg register. c) flag bit txif will not be set. d) when the first word has been shifted out of tsr, the txreg register will transfer the second word to the tsr and flag bit txif will be set. e) if enable bit txie is set, the interrupt will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. steps to follow when setting up a synchronous slave transmission: 1. enable the synchronous slave serial port by setting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 18.4.2 usart synchronous slave reception the operation of the synchronous master and slave modes is identical, except in the case of the sleep mode and bit sren, which is a ?don?t care? in slave mode. if receive is enabled by setting bit cren prior to the sleep instruction, then a word may be received during sleep. on completely receiving the word, the rsr register will transfer the data to the rcreg register and if enable bit rcie bit is set, the interrupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. steps to follow when setting up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set enable bit rcie. 3. if 9-bit reception is desired, set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rcif will be set when reception is complete. an interrupt will be generated if enable bit rcie was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing bit cren. ? 2006 microchip technology inc. ds41159e-page 197 pic18fxx8 table 18-10: registers associated with synchronous slave transmission table 18-11: registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000u txreg usart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used fo r synchronous slave transmission. note 1: these registers or register bits are not im plemented on the pic18f248 and pic18f258 and read as ? 0 ?s. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000u rcreg usart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave reception. note 1: these registers or register bits are not implemented on the pic18f248 and pic18f258 and read as ? 0 ?s. pic18fxx8 ds41159e-page 198 ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. ds41159e-page 199 pic18fxx8 19.0 can module 19.1 overview the controller area network (can) module is a serial interface, useful for communicating with other peripher- als or microcontroller devices. this interface/protocol was designed to allow communications within noisy environments. the can module is a communication controller, implementing the can 2.0 a/b protocol as defined in the bosch specification. the module will support can 1.2, can 2.0a, can 2.0b passive and can 2.0b active versions of the protocol. the module implemen- tation is a full can system. the can specification is not covered within this data sheet. the reader may refer to the bosch can specification for further details. the module features are as follows: ? complies with iso can conformance test ? implementation of the can protocol can 1.2, can 2.0a and can 2.0b ? standard and extended data frames ? 0-8 bytes data length ? programmable bit rate up to 1 mbit/sec ? support for remote frames ? double-buffered receiver with two prioritized received message storage buffers ? 6 full (standard/extended identifier) acceptance filters, 2 associated with the high priority receive buffer and 4 associated with the low priority receive buffer ? 2 full acceptance filter masks, one each associated with the high and low priority receive buffers ? three transmit buffers with application specified prioritization and abort capability ? programmable wake-up functionality with integrated low-pass filter ? programmable loopback mode supports self-test operation ? signaling via interrupt capabilities for all can receiver and transmitter error states ? programmable clock source ? programmable link to timer module for time-stamping and network synchronization ? low-power sleep mode 19.1.1 overview of the module the can bus module consists of a protocol engine and message buffering and control. the can protocol engine handles all functions for receiving and transmit- ting messages on the can bus. messages are transmitted by first loading the appropriate data registers. status and errors can be checked by reading the appropriate registers. any message detected on the can bus is checked for errors and then matched against filters to see if it should be received and stored in one of the 2 receive registers. the can module supports the following frame types: ? standard data frame ? extended data frame ? remote frame ? error frame ? overload frame reception ? interframe space can module uses rb3/canrx and rb2/cantx/int2 pins to interface with can bus. in order to configure canrx and cantx as can interface: ? bit trisb<3> must be set; ? bit trisb<2> must be cleared. 19.1.2 transmit/receive buffers the pic18fxx8 has three transmit and two receive buffers, two acceptance masks (one for each receive buffer) and a total of six acceptance filters. figure 19-1 is a block diagram of these buffers and their connection to the protocol engine. pic18fxx8 ds41159e-page 200 ? 2006 microchip technology inc. figure 19-1: can buffers and protocol engine block diagram acceptance mask rxm0 acceptance filter rxf0 acceptance filter rxf1 message queue control transmit byte sequencer txreq txb0 txabt txlarb txerr txbuff message receive shift receive error transmit error rxerrcnt txerrcnt err-pas bus-off counter counter transmit logic bit timing logic tx rx bit timing generator protocol engine buffers transmit shift protocol fsm comparator crc register txreq txb1 txabt txlarb txerr txbuff message txreq txb2 txabt txlarb txerr txbuff message message assembly buffer acceptance filter rxm2 acceptance filter rxf3 acceptance filter rxf4 acceptance filter rxf5 acceptance mask rxm1 rxb0 rxb1 accept accept message request data and identifier data and identifier identifier identifier ? 2006 microchip technology inc. ds41159e-page 201 pic18fxx8 19.2 can module registers there are many control and data registers associated with the can module. for convenience, their descriptions have been grouped into the following sections: ? control and status registers ? transmit buffer registers (data and control) ? receive buffer registers (data and control) ? baud rate control registers ? i/o control register ? interrupt status and control registers 19.2.1 can control and status registers the registers described in this section control the overall operation of the can module and show its operational status. register 19-1: cancon: can control regist er note: not all can registers are available in the access bank. r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 reqop2 reqop1 reqop0 abat win2 win1 win0 ? bit 7 bit 0 bit 7-5 reqop2:reqop0: request can operation mode bits 1xx = request configuration mode 011 = request listen only mode 010 = request loopback mode 001 = request disable mode 000 = request normal mode bit 4 abat: abort all pending transmissions bit 1 = abort all pending transmissions (in all transmit buffers) 0 = transmissions proceeding as normal bit 3-1 win2:win0: window address bits this selects which of the can buffers to switch into the access bank area. this allows access to the buffer registers from any data memory bank. after a frame has caused an interrupt, the icode2:icode0 bits can be copied to the win2:win0 bits to select the correct buffer. see example 19-1 for code example. 111 = receive buffer 0 110 = receive buffer 0 101 = receive buffer 1 100 = transmit buffer 0 011 = transmit buffer 1 010 = transmit buffer 2 001 = receive buffer 0 000 = receive buffer 0 bit 0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 202 ? 2006 microchip technology inc. register 19-2: canstat: can status register r-1 r-0 r-0 u-0 r-0 r-0 r-0 u-0 opmode2 opmode1 opmode0 ? icode2 icode1 icode0 ? bit 7 bit 0 bit 7-5 opmode2:opmode0: operation mode status bits 111 = reserved 110 = reserved 101 = reserved 100 = configuration mode 011 = listen only mode 010 = loopback mode 001 = disable mode 000 = normal mode note: before the device goes into sleep mode, select disable mode. bit 4 unimplemented: read as ? 0 ? bit 3-1 icode2:icode0: interrupt code bits when an interrupt occurs, a prioritized coded interrupt value will be present in the icode2:icode0 bits. these codes indicate the source of the interrupt. the icode2:icode0 bits can be copied to the win2:win0 bits to select the correct buffer to map into the access bank area. see example 19-1 for code example. 111 = wake-up on interrupt 110 = rxb0 interrupt 101 = rxb1 interrupt 100 = txb0 interrupt 011 = txb1 interrupt 010 = txb2 interrupt 001 = error interrupt 000 = no interrupt bit 0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 203 pic18fxx8 example 19-1: win and icode bits usage in interrupt service routine to access tx/rx buffers ; save application required context. ; poll interrupt flags and determine source of interrupt ; this was found to be can interrupt ; tempcancon and tempcanstat are variables defined in access bank low movff cancon, tempcancon ; save cancon.win bits ; this is required to prevent cancon ; from corrupting can buffer access ; in-progress while this interrupt ; occurred movff canstat, tempcanstat ; save canstat register ; this is required to make sure that ; we use same canstat value rather ; than one changed by another can ; interrupt. movf tempcanstat, w ; retrieve icode bits andlw b?00001110? addwf pcl, f ; perform computed goto ; to corresponding interrupt cause bra nointerrupt ; 000 = no interrupt bra errorinterrupt ; 001 = error interrupt bra txb2interrupt ; 010 = txb2 interrupt bra txb1interrupt ; 011 = txb1 interrupt bra txb0interrupt ; 100 = txb0 interrupt bra rxb1interrupt ; 101 = rxb1 interrupt bra rxb0interrupt ; 110 = rxb0 interrupt ; 111 = wake-up on interrupt wakeupinterrupt bcf pir3, wakif ; clear the interrupt flag ; ; user code to handle wake-up procedure ; ; ; continue checking for other interrupt source or return from here ? nointerrupt ? ; pc should never vector here. user may ; place a trap such as infinite loop or pin/port ; indication to catch this error. errorinterrupt bcf pir3, errif ; clear the interrupt flag ? ; handle error. retfie txb2interrupt bcf pir3, txb2if ; clear the interrupt flag goto accessbuffer txb1interrupt bcf pir3, txb1if ; clear the interrupt flag goto accessbuffer txb0interrupt bcf pir3, txb0if ; clear the interrupt flag goto accessbuffer rxb1interrupt bcf pir3, rxb1if ; clear the interrupt flag goto accessbuffer pic18fxx8 ds41159e-page 204 ? 2006 microchip technology inc. example 19-1: win and icode bits usage in interrupt service routine to access tx/rx buffers (continued) rxb0interrupt bcf pir3, rxb0if ; clear the interrupt flag goto accessbuffer accessbuffer ; this is either tx or rx interrupt ; copy cancon.icode bits to canstat.win bits movf cancon, w ; clear cancon.win bits before copying ; new ones. andlw b?11110001? ; use previously saved cancon value to ; make sure same value. movwf cancon ; copy masked value back to tempcancon movf tempcanstat, w ; retrieve icode bits andlw b?00001110? ; use previously saved canstat value ; to make sure same value. iorwf cancon ; copy icode bits to win bits. ; copy the result to actual cancon ; access current buffer? ; user code ; restore cancon.win bits movf cancon, w ; preserve current non win bits andlw b?11110001? iorwf tempcancon, w ; restore original win bits movwf cancon ; do not need to restore canstat - it is read-only register. ; return from interrupt or check for another module interrupt source ? 2006 microchip technology inc. ds41159e-page 205 pic18fxx8 register 19-3: comstat: communication stat us register r/c-0 r/c-0 r-0 r-0 r-0 r-0 r-0 r-0 rxb0ovfl rxb1ovfl txbo txbp rxbp txwarn rxwarn ewarn bit 7 bit 0 bit 7 rxb0ovfl: receive buffer 0 overflow bit 1 = receive buffer 0 overflowed 0 = receive buffer 0 has not overflowed bit 6 rxb1ovfl: receive buffer 1 overflow bit 1 = receive buffer 1 overflowed 0 = receive buffer 1 has not overflowed bit 5 txbo: transmitter bus-off bit 1 = transmit error counter > 255 0 = transmit error counter 255 bit 4 txbp: transmitter bus passive bit 1 = transmission error counter > 127 0 = transmission error counter 127 bit 3 rxbp: receiver bus passive bit 1 = receive error counter > 127 0 = receive error counter 127 bit 2 txwarn: transmitter warning bit 1 = 127 transmit error counter > 95 0 = transmit error counter 95 bit 1 rxwarn: receiver warning bit 1 = 127 receive error counter > 95 0 = receive error counter 95 bit 0 ewarn: error warning bit this bit is a flag of the rxwarn and txwarn bits. 1 = the rxwarn or the txwarn bits are set 0 = neither the rxwarn or the txwarn bits are set legend: r = readable bit w = writable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 206 ? 2006 microchip technology inc. 19.2.2 can transmit buffer registers this section describes the can transmit buffer registers and their associated control registers. register 19-4: txbncon: transmit buffer n co ntrol registers u-0 r-0 r-0 r-0 r/w-0 u-0 r/w-0 r/w-0 ? txabt txlarb txerr txreq ? txpri1 txpri0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 txabt: transmission aborted status bit 1 = message was aborted 0 = message was not aborted bit 5 txlarb: transmission lost arbitration status bit 1 = message lost arbitration while being sent 0 = message did not lose arbitration while being sent bit 4 txerr: transmission error detected status bit 1 = a bus error occurred while the message was being sent 0 = a bus error did not occur while the message was being sent bit 3 txreq: transmit request status bit 1 = requests sending a message. clears the txabt, txlarb and txerr bits. 0 = automatically cleared when the message is successfully sent note: clearing this bit in software while the bit is set will request a message abort. bit 2 unimplemented: read as ? 0 ? bit 1-0 txpri1:txpri0: transmit priority bits 11 = priority level 3 (highest priority) 10 = priority level 2 01 = priority level 1 00 = priority level 0 (lowest priority) note: these bits set the order in which the transmit buffer will be transferred. they do not alter the can message identifier. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 207 pic18fxx8 register 19-5: txbnsidh: transmit buffer n standard identifier, high byte registers register 19-6: txbnsidl: transmit buffer n standard identifier, low byte registers register 19-7: txbneidh: transmit buffer n extended identifier, high byte registers r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 bit 7 bit 0 bit 7-0 sid10:sid3: standard identifier bits if exide = 0 (txbnsid register) or extended identifier bits eid28:eid21 if exide = 1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid2 sid1 sid0 ? exide ?eid17eid16 bit 7 bit 0 bit 7-5 sid2:sid0: standard identifier bits if exide = 0 or extended identifier bits eid20:eid18 if exide = 1 bit 4 unimplemented: read as ? 0 ? bit 3 exide: extended identifier enable bit 1 = message will transmit extended id, sid10:sid0 becomes eid28:eid18 0 = message will transmit standard id, eid17:eid0 are ignored bit 2 unimplemented: read as ? 0 ? bit 1-0 eid17:eid16: extended identifier bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 bit 7 bit 0 bit 7-0 eid15:eid8: extended identifier bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 208 ? 2006 microchip technology inc. register 19-8: txbneidl: transmit buffer n extended identifier, low byte registers register 19-9: txbndm: transmit buffer n data field byte m registers r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 bit 7 bit 0 bit 7-0 eid7:eid0: extended identifier bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x txbndm7 txbndm6 txbndm5 txbndm4 txbndm3 txbndm2 txbndm1 txbndm0 bit 7 bit 0 bit 7-0 txbndm7:txbndm0: transmit buffer n data field byte m bits (where 0 n < 3 and 0 < m < 8) each transmit buffer has an array of registers. for example, transmit buffer 0 has 7 registers: txb0d0 to txb0d7. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 209 pic18fxx8 register 19-10: txbndlc: transmit buffer n data length code registers register 19-11: txerrcnt: transmit error count register u-0 r/w-x u-0 u-0 r/w-x r/w-x r/w-x r/w-x ?txrtr ? ? dlc3 dlc2 dlc1 dlc0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 txrtr: transmission frame remote transmission request bit 1 = transmitted message will have txrtr bit set 0 = transmitted message will have txrtr bit cleared bit 5-4 unimplemented: read as ? 0 ? bit 3-0 dlc3:dlc0: data length code bits 1111 = reserved 1110 = reserved 1101 = reserved 1100 = reserved 1011 = reserved 1010 = reserved 1001 = reserved 1000 = data length = 8 bytes 0111 = data length = 7 bytes 0110 = data length = 6 bytes 0101 = data length = 5 bytes 0100 = data length = 4 bytes 0011 = data length = 3 bytes 0010 = data length = 2 bytes 0001 = data length = 1 bytes 0000 = data length = 0 bytes legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 bit 7 bit 0 bit 7-0 tec7:tec0: transmit error counter bits this register contains a value which is derived from the rate at which errors occur. when the error count overflows, the bus-off state occurs. when the bus has 128 occurrences of 11 consecutive recessive bits, the counter value is cleared. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 210 ? 2006 microchip technology inc. 19.2.3 can receive buffer registers this section shows the receive buffer registers with their associated control registers. register 19-12: rxb0con: receive buffer 0 control register r/c-0 r/w-0 r/w-0 u-0 r-0 r/w-0 r-0 r-0 rxful (1) rxm1 (1) rxm0 (1) ? rxrtrro rxb0dben jtoff filhit0 bit 7 bit 0 bit 7 rxful: receive full status bit (1) 1 = receive buffer contains a received message 0 = receive buffer is open to receive a new message note: this bit is set by the can module and must be cleared by software after the buffer is read. bit 6-5 rxm1:rxm0: receive buffer mode bits (1) 11 = receive all messages (including those with errors) 10 = receive only valid messages with extended identifier 01 = receive only valid messages with standard identifier 00 = receive all valid messages bit 4 unimplemented: read as ? 0 ? bit 3 rxrtrro: receive remote transfer request read-only bit 1 = remote transfer request 0 = no remote transfer request bit 2 rxb0dben: receive buffer 0 double-buffer enable bit 1 = receive buffer 0 overflow will write to receive buffer 1 0 = no receive buffer 0 overflow to receive buffer 1 bit 1 jtoff: jump table offset bit (read-only copy of rxb0dben) 1 = allows jump table offset between 6 and 7 0 = allows jump table offset between 1 and 0 note: this bit allows same filter jump table for both rxb0con and rxb1con. bit 0 filhit0: filter hit bit this bit indicates which acceptance filter enabled the message reception into receive buffer 0. 1 = acceptance filter 1 (rxf1) 0 = acceptance filter 0 (rxf0) note 1: bits rxful, rxm1 and rxm0 of rxb0con are not mirrored in rxb1con. legend: r = readable bit w = writable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 211 pic18fxx8 register 19-13: rxb1con: receive buffer 1 control register r/c-0 r/w-0 r/w-0 u-0 r-0 r-0 r-0 r-0 rxful (1) rxm1 (1) rxm0 (1) ? rxrtrro filhit2 filhit1 filhit0 bit 7 bit 0 bit 7 rxful: receive full status bit (1) 1 = receive buffer contains a received message 0 = receive buffer is open to receive a new message note: this bit is set by the can module and should be cleared by software after the buffer is read. bit 6-5 rxm1:rxm0: receive buffer mode bits (1) 11 = receive all messages (including those with errors) 10 = receive only valid messages with extended identifier 01 = receive only valid messages with standard identifier 00 = receive all valid messages bit 4 unimplemented: read as ? 0 ? bit 3 rxrtrro: receive remote transfer request bit (read-only) 1 = remote transfer request 0 = no remote transfer request bit 2-0 filhit2:filhit0: filter hit bits these bits indicate which acceptance filter enabled the last message reception into receive buffer 1. 111 = reserved 110 = reserved 101 = acceptance filter 5 (rxf5) 100 = acceptance filter 4 (rxf4) 011 = acceptance filter 3 (rxf3) 010 = acceptance filter 2 (rxf2) 001 = acceptance filter 1 (rxf1), only possible when rxb0dben bit is set 000 = acceptance filter 0 (rxf0), only possible when rxb0dben bit is set note 1: bits rxful, rxm1 and rxm0 of rxb1con are not mirrored in rxb0con. legend: r = readable bit w = writable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 212 ? 2006 microchip technology inc. register 19-14: rxbnsidh: receive buffer n standard identifier, high byte registers register 19-15: rxbnsidl: receive buffer n standard identifier, low byte registers register 19-16: rxbneidh: receive buffer n extended identifier, high byte registers r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 bit 7 bit 0 bit 7-0 sid10:sid3: standard identifier bits if exid = 0 (rxbnsidl register) or extended identifier bits eid28:eid21 if exid = 1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x u-0 r/w-x r/w-x sid2 sid1 sid0 srr exid ?eid17eid16 bit 7 bit 0 bit 7-5 sid2:sid0: standard identifier bits if exid = 0 or extended identifier bits eid20:eid18 if exid = 1 bit 4 srr: substitute remote request bit this bit is always ? 0 ? when exid = 1 or equal to the value of rxrtrro (rxnbcon<3>) when exid = 0 . bit 3 exid: extended identifier bit 1 = received message is an extended data frame, sid10:sid0 are eid28:eid18 0 = received message is a standard data frame bit 2 unimplemented: read as ? 0 ? bit 1-0 eid17:eid16: extended identifier bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 bit 7 bit 0 bit 7-0 eid15:eid8: extended identifier bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 213 pic18fxx8 register 19-17: rxbneidl: receive buffer n extended identifier, low byte registers register 19-18: rxbndlc: receive buffer n data length code registers r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 bit 7 bit 0 bit 7-0 eid7:eid0: extended identifier bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? rxrtr rb1 rb0 dlc3 dlc2 dlc1 dlc0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 rxrtr: receiver remote transmission request bit 1 = remote transfer request 0 = no remote transfer request bit 5 rb1: reserved bit 1 reserved by can spec and read as ? 0 ?. bit 4 rb0: reserved bit 0 reserved by can spec and read as ? 0 ?. bit 3-0 dlc3:dlc0: data length code bits 1111 = invalid 1110 = invalid 1101 = invalid 1100 = invalid 1011 = invalid 1010 = invalid 1001 = invalid 1000 = data length = 8 bytes 0111 = data length = 7 bytes 0110 = data length = 6 bytes 0101 = data length = 5 bytes 0100 = data length = 4 bytes 0011 = data length = 3 bytes 0010 = data length = 2 bytes 0001 = data length = 1 bytes 0000 = data length = 0 bytes legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 214 ? 2006 microchip technology inc. register 19-19: rxbndm: receive buffer n data field byte m registers register 19-20: rxerrcnt: receive error count register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x rxbndm7 rxbndm6 rxbndm5 rxbndm4 r xbndm3 rxbndm2 rxbndm1 rxbndm0 bit 7 bit 0 bit 7-0 rxbndm7:rxbndm0: receive buffer n data field byte m bits (where 0 n < 1 and 0 < m < 7) each receive buffer has an array of registers. for example, receive buffer 0 has 8 registers: rxb0d0 to rxb0d7. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 bit 7 bit 0 bit 7-0 rec7:rec0: receive error counter bits this register contains the receive error value as defined by the can specifications. when rxerrcnt > 127, the module will go into an error passive state. rxerrcnt does not have the ability to put the module in ?bus-off? state. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 215 pic18fxx8 19.2.3.1 message acceptance filters and masks this subsection describes the message acceptance filters and masks for the can receive buffers. register 19-21: rxfnsidh: receive acceptance filter n standard identifier filter, high byte registers register 19-22: rxfnsidl: receive acceptance filter n standard identifier filter, low byte registers r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 bit 7 bit 0 bit 7-0 sid10:sid3: standard identifier filter bits if exiden = 0 or extended identifier filter bits eid28:eid21 if exiden = 1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x u-0 r/w-x u-0 r/w-x r/w-x sid2 sid1 sid0 ? exiden ?eid17eid16 bit 7 bit 0 bit 7-5 sid2:sid0: standard identifier filter bits if exiden = 0 or extended identifier filter bits eid20:eid18 if exiden = 1 bit 4 unimplemented: read as ? 0 ? bit 3 exiden: extended identifier filter enable bit 1 = filter will only accept extended id messages 0 = filter will only accept standard id messages bit 2 unimplemented: read as ? 0 ? bit 1-0 eid17:eid16: extended identifier filter bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 216 ? 2006 microchip technology inc. register 19-23: rxfneidh: receive acceptance filter n extended identifier, high byte registers register 19-24: rxfneidl: receive acceptance filter n extended identifier, low byte registers register 19-25: rxmnsidh: receive acceptance mask n standard identifier mask, high byte registers r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 bit 7 bit 0 bit 7-0 eid15:eid8: extended identifier filter bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 bit 7 bit 0 bit 7-0 eid7:eid0: extended identifier filter bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 bit 7 bit 0 bit 7-0 sid10:sid3: standard identifier mask bits or extended identifier mask bits eid28:eid21 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 217 pic18fxx8 register 19-26: rxmnsidl: receive acceptance mask n standard identifier mask, low byte registers register 19-27: rxmneidh: receive acceptance mask n extended identifier mask, high byte registers register 19-28: rxmneidl: receive acceptance mask n extended identifier mask, low byte registers r/w-x r/w-x r/w-x u-0 u-0 u-0 r/w-x r/w-x sid2 sid1 sid0 ? ? ?eid17eid16 bit 7 bit 0 bit 7-5 sid2:sid0: standard identifier mask bits or extended identifier mask bits eid20:eid18 bit 4-2 unimplemented: read as ? 0 ? bit 1-0 eid17:eid16: extended identifier mask bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 bit 7 bit 0 bit 7-0 eid15:eid8: extended identifier mask bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 bit 7 bit 0 bit 7-0 eid7:eid0: extended identifier mask bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 218 ? 2006 microchip technology inc. 19.2.4 can baud rate registers this subsection describes the can baud rate registers. register 19-29: brgcon1: baud rate contro l register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 bit 7 bit 0 bit 7-6 sjw1:sjw0: synchronized jump width bits 11 = synchronization jump width time = 4 x t q 10 = synchronization jump width time = 3 x t q 01 = synchronization jump width time = 2 x t q 00 = synchronization jump width time = 1 x t q bit 5-0 brp5:brp0: baud rate prescaler bits 111111 = t q = (2 x 64)/f osc 111110 = t q = (2 x 63)/f osc : : 000001 = t q = (2 x 2)/f osc 000000 = t q = (2 x 1)/f osc legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: this register is accessible in configuration mode only. ? 2006 microchip technology inc. ds41159e-page 219 pic18fxx8 register 19-30: brgcon2: baud rate contro l register 2 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 seg2phts sam seg1ph2 seg1ph1 seg1ph0 prseg2 prseg1 prseg0 bit 7 bit 0 bit 7 seg2phts: phase segment 2 time select bit 1 = freely programmable 0 = maximum of pheg1 or information processing time (ipt), whichever is greater bit 6 sam: sample of the can bus line bit 1 = bus line is sampled three times prior to the sample point 0 = bus line is sampled once at the sample point bit 5-3 seg1ph2:seg1ph0: phase segment 1 bits 111 = phase segment 1 time = 8 x t q 110 = phase segment 1 time = 7 x t q 101 = phase segment 1 time = 6 x t q 100 = phase segment 1 time = 5 x t q 011 = phase segment 1 time = 4 x t q 010 = phase segment 1 time = 3 x t q 001 = phase segment 1 time = 2 x t q 000 = phase segment 1 time = 1 x t q bit 2-0 prseg2:prseg0: propagation time select bits 111 = propagation time = 8 x t q 110 = propagation time = 7 x t q 101 = propagation time = 6 x t q 100 = propagation time = 5 x t q 011 = propagation time = 4 x t q 010 = propagation time = 3 x t q 001 = propagation time = 2 x t q 000 = propagation time = 1 x t q legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: this register is accessible in configuration mode only. pic18fxx8 ds41159e-page 220 ? 2006 microchip technology inc. register 19-31: brgcon3: baud rate contro l register 3 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? wakfil ? ? ? seg2ph2 (1) seg2ph1 (1) seg2ph0 (1) bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 wakfil: selects can bus line filter for wake-up bit 1 = use can bus line filter for wake-up 0 = can bus line filter is not used for wake-up bit 5-3 unimplemented: read as ? 0 ? bit 2-0 seg2ph2:seg2ph0: phase segment 2 time select bits (1) 111 = phase segment 2 time = 8 x t q 110 = phase segment 2 time = 7 x t q 101 = phase segment 2 time = 6 x t q 100 = phase segment 2 time = 5 x t q 011 = phase segment 2 time = 4 x t q 010 = phase segment 2 time = 3 x t q 001 = phase segment 2 time = 2 x t q 000 = phase segment 2 time = 1 x t q note 1: ignored if seg2phts bit (brgcon2<7>) is clear. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 221 pic18fxx8 19.2.5 can module i/o control register this register controls the operation of the can module?s i/o pins in relation to the rest of the microcontroller. register 19-32: ciocon: can i/o control register u-0 u-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? ? endrhi cancap ? ? ? ? bit 7 bit 0 bit 7-6 unimplemented : read as ? 0 ? bit 5 endrhi: enable drive high bit 1 = cantx pin will drive v dd when recessive 0 = cantx pin will tri-state when recessive bit 4 cancap: can message receive capture enable bit 1 = enable can capture, can message receive signal replaces input on rc2/ccp1 0 = disable can capture, rc2/ccp1 input to ccp1 module bit 3-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 222 ? 2006 microchip technology inc. 19.2.6 can interrupt registers the registers in this section are the same as described in section 8.0 ?interrupts? . they are duplicated here for convenience. register 19-33: pir3: peripheral interrupt request (flag) register 3 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 irxif wakif errif txb2if txb1if txb0if rxb1if rxb0if bit 7 bit 0 bit 7 irxif: can invalid received message interrupt flag bit 1 = an invalid message has occurred on the can bus 0 = no invalid message on can bus bit 6 wakif: can bus activity wake-up interrupt flag bit 1 = activity on can bus has occurred 0 = no activity on can bus bit 5 errif: can bus error interrupt flag bit 1 = an error has occurred in the can module (multiple sources) 0 = no can module errors bit 4 txb2if: can transmit buffer 2 interrupt flag bit 1 = transmit buffer 2 has completed transmission of a message and may be reloaded 0 = transmit buffer 2 has not completed transmission of a message bit 3 txb1if: can transmit buffer 1 interrupt flag bit 1 = transmit buffer 1 has completed transmission of a message and may be reloaded 0 = transmit buffer 1 has not completed transmission of a message bit 2 txb0if: can transmit buffer 0 interrupt flag bit 1 = transmit buffer 0 has completed transmission of a message and may be reloaded 0 = transmit buffer 0 has not completed transmission of a message bit 1 rxb1if: can receive buffer 1 interrupt flag bit 1 = receive buffer 1 has received a new message 0 = receive buffer 1 has not received a new message bit 0 rxb0if: can receive buffer 0 interrupt flag bit 1 = receive buffer 0 has received a new message 0 = receive buffer 0 has not received a new message legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 223 pic18fxx8 register 19-34: pie3: peripheral interrupt enable register 3 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 irxie wakie errie txb2ie txb1ie txb0ie rxb1ie rxb0ie bit 7 bit 0 bit 7 irxie: can invalid received message interrupt enable bit 1 = enable invalid message received interrupt 0 = disable invalid message received interrupt bit 6 wakie: can bus activity wake-up interrupt enable bit 1 = enable bus activity wake-up interrupt 0 = disable bus activity wake-up interrupt bit 5 errie: can bus error interrupt enable bit 1 = enable can bus error interrupt 0 = disable can bus error interrupt bit 4 txb2ie: can transmit buffer 2 interrupt enable bit 1 = enable transmit buffer 2 interrupt 0 = disable transmit buffer 2 interrupt bit 3 txb1ie: can transmit buffer 1 interrupt enable bit 1 = enable transmit buffer 1 interrupt 0 = disable transmit buffer 1 interrupt bit 2 txb0ie: can transmit buffer 0 interrupt enable bit 1 = enable transmit buffer 0 interrupt 0 = disable transmit buffer 0 interrupt bit 1 rxb1ie: can receive buffer 1 interrupt enable bit 1 = enable receive buffer 1 interrupt 0 = disable receive buffer 1 interrupt bit 0 rxb0ie: can receive buffer 0 interrupt enable bit 1 = enable receive buffer 0 interrupt 0 = disable receive buffer 0 interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 224 ? 2006 microchip technology inc. register 19-35: ipr3: peripheral interrupt priority register 3 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 irxip wakip errip txb2ip txb1ip txb0ip rxb1ip rxb0ip bit 7 bit 0 bit 7 irxip: can invalid received message interrupt priority bit 1 = high priority 0 = low priority bit 6 wakip: can bus activity wake-up interrupt priority bit 1 = high priority 0 = low priority bit 5 errip: can bus error interrupt priority bit 1 = high priority 0 = low priority bit 4 txb2ip: can transmit buffer 2 interrupt priority bit 1 = high priority 0 = low priority bit 3 txb1ip: can transmit buffer 1 interrupt priority bit 1 = high priority 0 = low priority bit 2 txb0ip: can transmit buffer 0 interrupt priority bit 1 = high priority 0 = low priority bit 1 rxb1ip: can receive buffer 1 interrupt priority bit 1 = high priority 0 = low priority bit 0 rxb0ip: can receive buffer 0 interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2006 microchip technology inc. ds41159e-page 225 pic18fxx8 table 19-1: can controller register map note 1: shaded registers are available in access bank low area while the rest are available in bank 15. 2: canstat register is repeated in these locations to simplify application firmware. unique names are given for each instance of the canstat register due to the microchip header file requirement. address name address name address name address name f7fh ? f5fh ? f3fh ? f1fh rxm1eidl f7eh ? f5eh canstatro1 (2) f3eh canstatro3 (2) f1eh rxm1eidh f7dh ? f5dh rxb1d7 f3dh txb1d7 f1dh rxm1sidl f7ch ? f5ch rxb1d6 f3ch txb1d6 f1ch rxm1sidh f7bh ? f5bh rxb1d5 f3bh txb1d5 f1bh rxm0eidl f7ah ? f5ah rxb1d4 f3ah txb1d4 f1ah rxm0eidh f79h ? f59h rxb1d3 f39h txb1d3 f19h rxm0sidl f78h ? f58h rxb1d2 f38h txb1d2 f18h rxm0sidh f77h ? f57h rxb1d1 f37h txb1d1 f17h rxf5eidl f76h txerrcnt f56h rxb1d0 f36h txb1d0 f16h rxf5eidh f75h rxerrcnt f55h rxb1dlc f35h txb1dlc f15h rxf5sidl f74h comstat f54h rxb1eidl f34h txb1eidl f14h rxf5sidh f73h ciocon f53h rxb1eidh f33h txb1eidh f13h rxf4eidl f72h brgcon3 f52h rxb1sidl f32h txb1sidl f12h rxf4eidh f71h brgcon2 f51h rxb1sidh f31h txb1sidh f11h rxf4sidl f70h brgcon1 f50h rxb1con f30h txb1con f10h rxf4sidh f6fh cancon f4fh ? f2fh ? f0fh rxf3eidl f6eh canstat f4eh canstatro2 (2) f2eh canstatro4 (2) f0eh rxf3eidh f6dh rxb0d7 f4dh txb0d7 f2dh txb2d7 f0dh rxf3sidl f6ch rxb0d6 f4ch txb0d6 f2ch txb2d6 f0ch rxf3sidh f6bh rxb0d5 f4bh txb0d5 f2 bh txb2d5 f0bh rxf2eidl f6ah rxb0d4 f4ah txb0d4 f2ah txb2d4 f0ah rxf2eidh f69h rxb0d3 f49h txb0d3 f29h txb2d3 f09h rxf2sidl f68h rxb0d2 f48h txb0d2 f28h txb2d2 f08h rxf2sidh f67h rxb0d1 f47h txb0d1 f27h txb2d1 f07h rxf1eidl f66h rxb0d0 f46h txb0d0 f26h txb2d0 f06h rxf1eidh f65h rxb0dlc f45h txb0dlc f25h txb2dlc f05h rxf1sidl f64h rxb0eidl f44h txb0eidl f24h txb2eidl f04h rxf1sidh f63h rxb0eidh f43h txb0eidh f23h txb2eidh f03h rxf0eidl f62h rxb0sidl f42h txb0sidl f22h txb2sidl f02h rxf0eidh f61h rxb0sidh f41h txb0sidh f21h txb2sidh f01h rxf0sidl f60h rxb0con f40h txb0con f20h txb2con f00h rxf0sidh pic18fxx8 ds41159e-page 226 ? 2006 microchip technology inc. 19.3 can modes of operation the pic18fxx8 has six main modes of operation: ? configuration mode ? disable mode ? normal operation mode ? listen only mode ? loopback mode ? error recognition mode all modes, except error recognition, are requested by setting the reqop bits (cancon<7:5>); error recog- nition is requested through the rxm bits of the receive buffer register(s). entry into a mode is acknowledged by monitoring the opmode bits. when changing modes, the mode will not actually change until all pending message transmissions are complete. because of this, the user must verify that the device has actually changed into the requested mode before further operations are executed. 19.3.1 configuration mode the can module has to be initialized before the activation. this is only possible if the module is in the configuration mode. the configuration mode is requested by setting the reqop2 bit. only when the opmode2 status bit has a high level can the initializa- tion be performed. afterwards, the configuration registers, the acceptance mask registers and the acceptance filter registers can be written. the module is activated by setting the reqop control bits to zero. the module will protect the user from accidentally violating the can protocol through programming errors. all registers which control the configuration of the module can not be modified while the module is on- line. the can module will not be allowed to enter the configuration mode while a transmission is taking place. the config bit serves as a lock to protect the following registers. ? configuration registers ? bus timing registers ? identifier acceptance filter registers ? identifier acceptance mask registers in the configuration mode, the module will not transmit or receive. the error counters are cleared and the interrupt flags remain unchanged. the programmer will have access to configuration registers that are access restricted in other modes. 19.3.2 disable mode in disable mode, the module will not transmit or receive. the module has the ability to set the wakif bit due to bus activity, however, any pending interrupts will remain and the error counters will retain their value. if reqop<2:0> is set to ? 001 ?, the module will enter the module disable mode. this mode is similar to disabling other peripheral modules by turning off the module enables. this causes the module internal clock to stop unless the module is active (i.e., receiving or transmit- ting a message). if the module is active, the module will wait for 11 recessive bits on the can bus, detect that condition as an idle bus, then accept the module disable command. opmode<2:0> = 001 indicates whether the module successfully went into module disable mode. the wakif interrupt is the only module interrupt that is still active in the module disable mode. if the wakie is set, the processor will receive an interrupt whenever the can bus detects a dominant state, as occurs with a sof. if the processor receives an interrupt while it is sleeping, more than one message may get lost. user firmware must anticipate this condition and request retransmission. if the processor is running while it receives an interrupt, only the first message may get lost. the i/o pins will revert to normal i/o function when the module is in the module disable mode. 19.3.3 normal mode this is the standard operating mode of the pic18fxx8. in this mode, the device actively monitors all bus messages and generates acknowledge bits, error frames, etc. this is also the only mode in which the pic18fxx8 will transmit messages over the can bus. 19.3.4 listen only mode listen only mode provides a means for the pic18fxx8 to receive all messages, including messages with errors. this mode can be used for bus monitor applications or for detecting the baud rate in ?hot plugging? situations. for auto-baud detection, it is necessary that there are at least two other nodes which are communicating with each other. the baud rate can be detected empirically by testing different values until valid messages are received. the listen only mode is a silent mode, meaning no messages will be trans- mitted while in this state, including error flags or acknowledge signals. the filters and masks can be used to allow only particular messages to be loaded into the receive registers, or the filter masks can be set to all zeros to allow a message with any identifier to pass. the error counters are reset and deactivated in this state. the listen only mode is activated by setting the mode request bits in the cancon register. ? 2006 microchip technology inc. ds41159e-page 227 pic18fxx8 19.3.5 loopback mode this mode will allow internal transmission of messages from the transmit buffers to the receive buffers without actually transmitting messages on the can bus. this mode can be used in system development and testing. in this mode, the ack bit is ignored and the device will allow incoming messages from itself, just as if they were coming from another node. the loopback mode is a silent mode, meaning no messages will be trans- mitted while in this state, including error flags or acknowledge signals. the txcan pin will revert to port i/o while the device is in this mode. the filters and masks can be used to allow only particular messages to be loaded into the receive registers. the masks can be set to all zeros to provide a mode that accepts all messages. the loopback mode is activated by setting the mode request bits in the cancon register. 19.3.6 error recognition mode the module can be set to ignore all errors and receive all message. the error recognition mode is activated by setting the rxm<1:0> bits in the rxbncon registers to ? 11 ?. in this mode, all messages, valid or invalid, are received and copied to the receive buffer. 19.4 can message transmission 19.4.1 transmit buffers the pic18fxx8 implements three transmit buffers (figure 19-2). each of these buffers occupies 14 bytes of sram and are mapped into the device memory map. for the mcu to have write access to the message buffer, the txreq bit must be clear, indicating that the message buffer is clear of any pending message to be transmitted. at a minimum, the txbnsidh, txbnsidl and txbndlc registers must be loaded. if data bytes are present in the message, the txbndm registers must also be loaded. if the message is to use extended identifiers, the txbneidm registers must also be loaded and the exide bit set. prior to sending the message, the mcu must initialize the txine bit to enable or disable the generation of an interrupt when the message is sent. the mcu must also initialize the txp priority bits (see section 19.4.2 ?transmit priority? ). 19.4.2 transmit priority transmit priority is a prioritization within the pic18fxx8 of the pending transmittable messages. this is independent from and not related to any prioriti- zation implicit in the message arbitration scheme built into the can protocol. prior to sending the sof, the priority of all buffers that are queued for transmission is compared. the transmit buffer with the highest priority will be sent first. if two buffers have the same priority setting, the buffer with the highest buffer number will be sent first. there are four levels of transmit priority. if txp bits for a particular message buffer are set to ? 11 ?, that buffer has the highest possible priority. if txp bits for a particular message buffer are ? 00 ?, that buffer has the lowest possible priority. figure 19-2: transmit buffer block diagram message queue control transmit byte sequencer txreq txb0 txabt txlarb txerr txbuff message txreq txb1 txabt txlarb txerr txbuff message txreq txb2 txabt txlarb txerr txbuff message message request pic18fxx8 ds41159e-page 228 ? 2006 microchip technology inc. 19.4.3 initiating transmission to initiate message transmission, the txreq bit must be set for each buffer to be transmitted. when txreq is set, the txabt, txlarb and txerr bits will be cleared. setting the txreq bit does not initiate a message transmission; it merely flags a message buffer as ready for transmission. transmission will start when the device detects that the bus is available. the device will then begin transmission of the highest priority message that is ready. when the transmission has completed successfully, the txreq bit will be cleared, the txbnif bit will be set and an interrupt will be generated if the txbnie bit is set. if the message transmission fails, the txreq will remain set, indicating that the message is still pending for transmission and one of the following condition flags will be set. if the message started to transmit but encountered an error condition, the txerr and the irxif bits will be set and an interrupt will be generated. if the message lost arbitration, the txlarb bit will be set. 19.4.4 aborting transmission the mcu can request to abort a message by clearing the txreq bit associated with the corresponding message buffer (txbncon<3>). setting the abat bit (cancon<4>) will request an abort of all pending messages. if the message has not yet started transmis- sion, or if the message started but is interrupted by loss of arbitration or an error, the abort will be processed. the abort is indicated when the module sets the abt bits for the corresponding buffer (txbncon<6>). if the message has started to transmit, it will attempt to transmit the current message fully. if the current message is transmitted fully and is not lost to arbitration or an error, the abt bit will not be set because the message was transmitted successfully. likewise, if a message is being transmitted during an abort request and the message is lost to arbitration or an error, the message will not be retransmitted and the abt bit will be set, indicating that the message was successfully aborted. ? 2006 microchip technology inc. ds41159e-page 229 pic18fxx8 figure 19-3: internal transmit message flowchart start is can bus available to start transmission? no examine txpri <1:0> to are any txreq bits = 1 ? the message transmission sequence begins when the device determines that the txreq for any of the transmit registers has been set. clear: txabt, txlarb and txerr yes is txreq = 0 abat = 1 ? clearing the txreq bit while it is set, or setting the abat bit before the message has started transmission, will abort the message. no begin transmission (sof) abort transmission: was message transmitted successfully? no yes set txreq = 0 is txie = 1 ? generate interrupt yes yes set txabt = 1 set set txerr = 1 ye s no determine highest priority message no is txlarb = 1 ? the txie bit determines if an inter- rupt should be generated when a message is successfully transmitted. end is txreq = 0 or txabt = 1 ? ye s no txbufe = 1 yes a message can also be aborted if a message error or lost arbitration condition occurred during transmission. arbitration lost during transmission no pic18fxx8 ds41159e-page 230 ? 2006 microchip technology inc. 19.5 message reception 19.5.1 receive message buffering the pic18fxx8 includes two full receive buffers with multiple acceptance filters for each. there is also a separate message assembly buffer (mab) which acts as a third receive buffer (see figure 19-4). 19.5.2 receive buffers of the three receive buffers, the mab is always commit- ted to receiving the next message from the bus. the remaining two receive buffers are called rxb0 and rxb1 and can receive a complete message from the protocol engine. the mcu can access one buffer while the other buffer is available for message reception or holding a previously received message. the mab assembles all messages received. these messages will be transferred to the rxbn buffers only if the acceptance filter criteria are met. when a message is moved into either of the receive buffers, the appropriate rxbnif bit is set. this bit must be cleared by the mcu when it has completed process- ing the message in the buffer in order to allow a new message to be received into the buffer. this bit provides a positive lockout to ensure that the mcu has finished with the message before the pic18fxx8 attempts to load a new message into the receive buffer. if the rxbnie bit is set, an interrupt will be generated to indicate that a valid message has been received. 19.5.3 receive priority rxb0 is the higher priority buffer and has two message acceptance filters associated with it. rxb1 is the lower priority buffer and has four acceptance filters associ- ated with it. the lower number of acceptance filters makes the match on rxb0 more restrictive and implies a higher priority for that buffer. additionally, the rxb0con register can be configured such if rxb0 contains a valid message and another valid message is received, an overflow error will not occur and the new message will be moved into rxb1 regardless of the acceptance criteria of rxb1. there are also two programmable acceptance filter masks available, one for each receive buffer (see section 19.6 ?message acceptance filters and masks? ). when a message is received, bits <3:0> of the rxbncon register will indicate the acceptance filter number that enabled reception and whether the received message is a remote transfer request. the rxm bits set special receive modes. normally, these bits are set to ? 00 ? to enable reception of all valid messages as determined by the appropriate accep- tance filters. in this case, the determination of whether or not to receive standard or extended messages is determined by the exide bit in the acceptance filter register. if the rxm bits are set to ? 01 ? or ? 10 ?, the receiver will accept only messages with standard or extended identifiers, respectively. if an acceptance filter has the exide bit set, such that it does not corre- spond with the rxm mode, that acceptance filter is rendered useless. these two modes of rxm bits can be used in systems where it is known that only standard or extended messages will be on the bus. if the rxm bits are set to ? 11 ?, the buffer will receive all messages regardless of the values of the acceptance filters. also, if a message has an error before the end of frame, that portion of the message assembled in the mab before the error frame will be loaded into the buffer. this mode has some value in debugging a can system and would not be used in an actual system environment. 19.5.4 time-stamping the can module can be programmed to generate a time-stamp for every message that is received. when enabled, the module generates a capture signal for ccp1 which in turns captures the value of either timer1 or timer3. this value can be used as the message time-stamp. to use the time-stamp capability, the cancap bit (ciocan<4>) must be set. this replaces the capture input for ccp1 with the signal generated from the can module. in addition, ccp1con<3:0> must be set to ? 0011 ? to enable the ccp special event trigger for can events. figure 19-4: receive buffer block diagram note: the entire contents of the mab are moved into the receive buffer once a message is accepted. this means that regardless of the type of identifier (standard or extended) and the number of data bytes received, the entire receive buffer is over- written with the mab contents. therefore, the contents of all registers in the buffer must be assumed to have been modified when any message is received. acceptance mask rxm0 acceptance filter rxf0 acceptance filter rxf1 message assembly buffer acceptance filter rxm2 acceptance filter rxf3 acceptance filter rxf4 acceptance filter rxf5 acceptance mask rxm1 rxb0 rxb1 accept accept data and identifier data and identifier identifier identifier ? 2006 microchip technology inc. ds41159e-page 231 pic18fxx8 figure 19-5: internal message reception flowchart start detect start of message? valid message received? generate error message identifier meets a filter criteria? is rxful = 0 ? go to start move message into rxb0 set rxrdy = 1 set filhit <2:0> is rxful = 0 ? move message into rxb1 set rxrdy = 1 yes, meets criteria for rxbo yes, meets criteria for rxb1 no generate interrupt yes ye s no no yes ye s no no yes yes frame the rxful bit determines if the receive register is empty and able to accept a new message. no yes no generate overrun error: begin loading message into message assembly buffer (mab) according to which filter criteria was met is rxie = 1 ? is rxie = 1 ? is rx0dben = 1 ? the rxb0dben bit determines if rxb0 can rollover into rxb1 if it is full. set rxb0ovfl generate overrun error: set rxb1ovfl is errie = 1 ? no go to start ye s no set filhit <0> according to which filter criteria was met set canstat <3:0> according to which receive buffer the message was loaded into pic18fxx8 ds41159e-page 232 ? 2006 microchip technology inc. 19.6 message acceptance filters and masks the message acceptance filters and masks are used to determine if a message in the message assembly buffer should be loaded into either of the receive buff- ers. once a valid message has been received into the mab, the identifier fields of the message are compared to the filter values. if there is a match, that message will be loaded into the appropriate receive buffer. the filter masks are used to determine which bits in the identifier are examined with the filters. a truth table is shown below in table 19-2 that indicates how each bit in the identifier is compared to the masks and filters to deter- mine if a message should be loaded into a receive buffer. the mask essentially determines which bits to apply the acceptance filters to. if any mask bit is set to a zero, then that bit will automatically be accepted regardless of the filter bit. table 19-2: filter/mask truth table as shown in the receive buffer block diagram (figure 19-4), acceptance filters rxf0 and rxf1 and filter mask rxm0 are associated with rxb0. filters rxf2, rxf3, rxf4 and rxf5 and mask rxm1 are associated with rxb1. when a filter matches and a message is loaded into the receive buffer, the filter number that enabled the message reception is loaded into the filhit bit(s). for rxb1, the rxb1con register contains the filhit<2:0> bits. they are coded as follows: ? 101 = acceptance filter 5 (rxf5) ? 100 = acceptance filter 4 (rxf4) ? 011 = acceptance filter 3 (rxf3) ? 010 = acceptance filter 2 (rxf2) ? 001 = acceptance filter 1 (rxf1) ? 000 = acceptance filter 0 (rxf0) the coding of the rxb0dben bit enables these three bits to be used similarly to the filhit bits and to distinguish a hit on filter rxf0 and rxf1, in either rxb0, or after a rollover into rxb1. ? 111 = acceptance filter 1 (rxf1) ? 110 = acceptance filter 0 (rxf0) ? 001 = acceptance filter 1 (rxf1) ? 000 = acceptance filter 0 if the rxb0dben bit is clear, there are six codes corresponding to the six filters. if the rxb0dben bit is set, there are six codes corresponding to the six filters plus two additional codes corresponding to rxf0 and rxf1 filters that rollover into rxb1. if more than one acceptance filter matches, the filhit bits will encode the binary value of the lowest numbered filter that matched. in other words, if filter rxf2 and filter rxf4 match, filhit will be loaded with the value for rxf2. this essentially prioritizes the acceptance filters with a lower number filter having higher priority. messages are compared to filters in ascending order of filter number. the mask and filter registers can only be modified when the pic18fxx8 is in configuration mode. the mask and filter registers cannot be read outside of configuration mode. when outside of configuration mode, all mask and filter registers will be read as ? 0 ?. figure 19-6: message acceptance mask and filter operation mask bit n filter bit n message identifier bit n001 accept or reject bit n 0x x accept 10 0 accept 10 1 reject 11 0 reject 11 1 accept legend: x = don?t care note: ? 000 ? and ? 001 ? can only occur if the rxb0dben bit is set in the rxb0con register allowing rxb0 messages to rollover into rxb1. acceptance filter register acceptance mask register rxrqst message assembly buffer rxfn 0 rxfn 1 rxfn n rxmn 0 rxmn 1 rxmn n identifier ? 2006 microchip technology inc. ds41159e-page 233 pic18fxx8 19.7 baud rate setting all nodes on a given can bus must have the same nominal bit rate. the can protocol uses non-return- to-zero (nrz) coding which does not encode a clock within the data stream. therefore, the receive clock must be recovered by the receiving nodes and synchronized to the transmitters clock. as oscillators and transmission time may vary from node to node, the receiver must have some type of phase lock loop (pll) synchronized to data transmis- sion edges to synchronize and maintain the receiver clock. since the data is nrz coded, it is necessary to include bit stuffing to ensure that an edge occurs at least every six bit times to maintain the digital phase lock loop (dpll) synchronization. the bit timing of the pic18fxx8 is implemented using a dpll that is configured to synchronize to the incoming data and provides the nominal timing for the transmitted data. the dpll breaks each bit time into multiple segments made up of minimal periods of time called the time quanta (t q ). bus timing functions executed within the bit time frame, such as synchronization to the local oscillator, network transmission delay compensation and sample point positioning, are defined by the programmable bit timing logic of the dpll. all devices on the can bus must use the same bit rate. however, all devices are not required to have the same master oscillator clock frequency. for the different clock frequencies of the individual devices, the bit rate has to be adjusted by appropriately setting the baud rate prescaler and number of time quanta in each segment. the nominal bit rate is the number of bits transmitted per second, assuming an ideal transmitter with an ideal oscillator, in the absence of resynchronization. the nominal bit rate is defined to be a maximum of 1 mb/s. the nominal bit time is defined as: t bit = 1/nominal bit rate the nominal bit time can be thought of as being divided into separate, non-overlapping time segments. these segments (figure 19-7) include: ? synchronization segment (sync_seg) ? propagation time segment (prop_seg) ? phase buffer segment 1 (phase_seg1) ? phase buffer segment 2 (phase_seg2) the time segments (and thus, the nominal bit time) are, in turn, made up of integer units of time called time quanta or t q (see figure 19-7). by definition, the nominal bit time is programmable from a minimum of 8t q to a maximum of 25 t q . also, by definition, the minimum nominal bit time is 1 s corresponding to a maximum 1 mb/s rate. the actual duration is given by the relationship: nominal bit time = t q * (sync_seg + prop_seg + phase_seg1 + phase_seg2) the time quantum is a fixed unit derived from the oscillator period. it is also defined by the programmable baud rate prescaler, with integer values from 1 to 64, in addition to a fixed divide-by-two for clock generation. mathematically, this is t q ( s) = (2 * (brp + 1))/f osc (mhz) or t q ( s) = (2 * (brp + 1)) * t osc ( s) where f osc is the clock frequency, t osc is the corresponding oscillator period and brp is an integer (0 through 63) represented by the binary values of brgcon1<5:0>. figure 19-7: bit time partitioning input sync propagation segment phase segment 1 phase segment 2 sample point t q nominal bit time bit time intervals signal segment pic18fxx8 ds41159e-page 234 ? 2006 microchip technology inc. 19.7.1 time quanta as already mentioned, the time quanta is a fixed unit derived from the oscillator period and baud rate prescaler. its relationship to t bit and the nominal bit rate is shown in example 19-2. example 19-2: calculating t q , nominal bit rate and nominal bit time the frequencies of the oscillators in the different nodes must be coordinated in order to provide a system wide specified nominal bit time. this means that all oscilla- tors must have a t osc that is an integral divisor of t q . it should also be noted that although the number of t q is programmable from 4 to 25, the usable minimum is 8t q . a bit time of less than 8 t q in length is not ensured to operate correctly. 19.7.2 synchronization segment this part of the bit time is used to synchronize the various can nodes on the bus. the edge of the input signal is expected to occur during the sync segment. the duration is 1 t q . 19.7.3 propagation segment this part of the bit time is used to compensate for physical delay times within the network. these delay times consist of the signal propagation time on the bus line and the internal delay time of the nodes. the length of the propagation segment can be programmed from 1t q to 8 t q by setting the prseg2:prseg0 bits. 19.7.4 phase buffer segments the phase buffer segments are used to optimally locate the sampling point of the received bit within the nominal bit time. the sampling point occurs between phase segment 1 and phase segment 2. these segments can be lengthened or shortened by the resynchronization process. the end of phase segment 1 determines the sampling point within a bit time. phase segment 1 is programmable from 1 t q to 8 t q in duration. phase segment 2 provides delay before the next transmitted data transition and is also programmable from 1 t q to 8 t q in duration. however, due to ipt requirements, the actual minimum length of phase segment 2 is 2 t q or it may be defined to be equal to the greater of phase segment 1 or the information processing time (ipt). 19.7.5 sample point the sample point is the point of time at which the bus level is read and the value of the received bit is deter- mined. the sampling point occurs at the end of phase segment 1. if the bit timing is slow and contains many t q , it is possible to specify multiple sampling of the bus line at the sample point. the value of the received bit is determined to be the value of the majority decision of three values. the three samples are taken at the sam- ple point and twice before, with a time of t q /2 between each sample. 19.7.6 information processing time the information processing time (ipt) is the time segment, starting at the sample point, that is reserved for calculation of the subsequent bit level. the can specification defines this time to be less than or equal to 2 t q . the pic18fxx8 defines this time to be 2 t q . thus, phase segment 2 must be at least 2 t q long. t q ( s) = (2 * (brp + 1))/f osc (mhz) t bit ( s) = t q ( s) * number of t q per bit interval nominal bit rate (bits/s) = 1/t bit case 1: for f osc = 16 mhz, brp<5:0> = 00h and nominal bit time = 8 t q : t q = (2 * 1)/16 = 0.125 s (125 ns) t bit = 8 * 0.125 = 1 s (10 -6 s) nominal bit rate = 1/10 -6 = 10 6 bits/s (1 mb/s) case 2: for f osc = 20 mhz, brp<5:0> = 01h and nominal bit time = 8 t q : t q = (2 * 2)/20 = 0.2 s (200 ns) t bit = 8 * 0.2 = 1.6 s (1.6 * 10 -6 s) nominal bit rate = 1/1.6 * 10 -6 s = 625,000 bits/s (625 kb/s) case 3: for f osc = 25 mhz, brp<5:0> = 3fh and nominal bit time = 25 t q : t q = (2 * 64)/25 = 5.12 s t bit = 25 * 5.12 = 128 s (1.28 * 10 -4 s) nominal bit rate = 1/1.28 * 10 -4 = 7813 bits/s (7.8 kb/s) ? 2006 microchip technology inc. ds41159e-page 235 pic18fxx8 19.8 synchronization to compensate for phase shifts between the oscillator frequencies of each of the nodes on the bus, each can controller must be able to synchronize to the relevant signal edge of the incoming signal. when an edge in the transmitted data is detected, the logic will compare the location of the edge to the expected time (sync_seg). the circuit will then adjust the values of phase segment 1 and phase segment 2, as necessary. there are two mechanisms used for synchronization. 19.8.1 hard synchronization hard synchronization is only done when there is a reces- sive to dominant edge during a bus idle condition, indi- cating the start of a message. after hard synchronization, the bit time counters are restarted with sync_seg. hard synchronization forces the edge which has occurred to lie within the synchronization segment of the restarted bit time. due to the rules of synchroniza- tion, if a hard synchronization occurs, there will not be a resynchronization within that bit time. 19.8.2 resynchronization as a result of resynchronization, phase segment 1 may be lengthened or phase segment 2 may be short- ened. the amount of lengthening or shortening of the phase buffer segments has an upper bound given by the synchronization jump width (sjw). the value of the sjw will be added to phase segment 1 (see figure 19-8) or subtracted from phase segment 2 (see figure 19-9). the sjw is programmable between 1 t q and 4 t q . clocking information will only be derived from reces- sive to dominant transitions. the property, that only a fixed maximum number of successive bits have the same value, ensures resynchronization to the bit stream during a frame. the phase error of an edge is given by the position of the edge relative to sync_seg, measured in t q . the phase error is defined in magnitude of t q as follows: ? e = 0 if the edge lies within sync_seg. ? e > 0 if the edge lies before the sample point. ? e < 0 if the edge lies after the sample point of the previous bit. if the magnitude of the phase error is less than or equal to the programmed value of the synchronization jump width, the effect of a resynchronization is the same as that of a hard synchronization. if the magnitude of the phase error is larger than the synchronization jump width and if the phase error is positive, then phase segment 1 is lengthened by an amount equal to the synchronization jump width. if the magnitude of the phase error is larger than the resynchronization jump width and if the phase error is negative, then phase segment 2 is shortened by an amount equal to the synchronization jump width. 19.8.3 synchronization rules ? only one synchronization within one bit time is allowed. ? an edge will be used for synchronization only if the value detected at the previous sample point (previously read bus value) differs from the bus value immediately after the edge. ? all other recessive to dominant edges, fulfilling rules 1 and 2, will be used for resynchronization with the exception that a node transmitting a dominant bit will not perform a resynchronization as a result of a recessive to dominant edge with a positive phase error. figure 19-8: lengthening a bit period (adding sjw to phase segment 1) input sync prop segment phase segment 1 phase segment 2 sjw sample point t q signal nominal bit length actual bit length bit time segments pic18fxx8 ds41159e-page 236 ? 2006 microchip technology inc. figure 19-9: shortening a bit period (subtracting sjw from phase segment 2) 19.9 programming time segments some requirements for programming of the time segments: ? prop seg + phase seg 1 phase seg 2 ? phase seg 2 sync jump width for example, assume that a 125 khz can baud rate is desired using 20 mhz for f osc . with a t osc of 50 ns, a baud rate prescaler value of 04h gives a t q of 500 ns. to obtain a nominal bit rate of 125 khz, the nominal bit time must be 8 s or 16 t q . using 1 t q for the sync segment, 2 t q for the propa- gation segment and 7 t q for phase segment 1 would place the sample point at 10 t q after the transition. this leaves 6 t q for phase segment 2. by the rules above, the sync jump width could be the maximum of 4 t q . however, normally a large sjw is only necessary when the clock generation of the differ- ent nodes is inaccurate or unstable, such as using ceramic resonators. typically, an sjw of 1 is enough. 19.10 oscillator tolerance as a rule of thumb, the bit timing requirements allow ceramic resonators to be used in applications with transmission rates of up to 125 kbit/sec. for the full bus speed range of the can protocol, a quartz oscillator is required. a maximum node-to-node oscillator variation of 1.7% is allowed. 19.11 bit timing configuration registers the configuration registers (brgcon1, brgcon2, brgcon3) control the bit timing for the can bus interface. these registers can only be modified when the pic18fxx8 is in configuration mode. 19.11.1 brgcon1 the brp bits control the baud rate prescaler. the sjw<1:0> bits select the synchronization jump width in terms of multiples of t q . 19.11.2 brgcon2 the prseg bits set the length of the propagation seg- ment in terms of t q . the seg1ph bits set the length of phase segment 1 in t q . the sam bit controls how many times the rxcan pin is sampled. setting this bit to a ? 1 ? causes the bus to be sampled three times; twice at t q /2 before the sample point and once at the normal sample point (which is at the end of phase segment 1). the value of the bus is determined to be the value read during at least two of the samples. if the sam bit is set to a ? 0 ?, then the rxcan pin is sampled only once at the sample point. the seg2phts bit controls how the length of phase segment 2 is determined. if this bit is set to a ? 1 ?, then the length of phase segment 2 is determined by the seg2ph bits of brgcon3. if the seg2phts bit is set to a ? 0 ?, then the length of phase segment 2 is the greater of phase segment 1 and the information processing time (which is fixed at 2 t q for the pic18fxx8). 19.11.3 brgcon3 the phseg2<2:0> bits set the length (in t q ) of phase segment 2 if the seg2phts bit is set to a ? 1 ?. if the seg2phts bit is set to a ? 0 ?, then the phseg2<2:0> bits have no effect. sync prop segment phase segment 1 phase segment 2 sjw t q sample point nominal bit length actual bit length ? 2006 microchip technology inc. ds41159e-page 237 pic18fxx8 19.12 error detection the can protocol provides sophisticated error detection mechanisms. the following errors can be detected. 19.12.1 crc error with the cyclic redundancy check (crc), the transmitter calculates special check bits for the bit sequence, from the start of a frame until the end of the data field. this crc sequence is transmitted in the crc field. the receiving node also calculates the crc sequence using the same formula and performs a comparison to the received sequence. if a mismatch is detected, a crc error has occurred and an error frame is generated. the message is repeated. 19.12.2 acknowledge error in the acknowledge field of a message, the transmitter checks if the acknowledge slot (which was sent out as a recessive bit) contains a dominant bit. if not, no other node has received the frame correctly. an acknowl- edge error has occurred; an error frame is generated and the message will have to be repeated. 19.12.3 form error if a node detects a dominant bit in one of the four segments, including end of frame, interframe space, acknowledge delimiter or crc delimiter, then a form error has occurred and an error frame is generated. the message is repeated. 19.12.4 bit error a bit error occurs if a transmitter sends a dominant bit and detects a recessive bit, or if it sends a recessive bit and detects a dominant bit, when monitoring the actual bus level and comparing it to the just transmitted bit. in the case where the transmitter sends a recessive bit and a dominant bit is detected during the arbitration field and the acknowledge slot, no bit error is generated because normal arbitration is occurring. 19.12.5 stuff bit error if, between the start of frame and the crc delimiter, six consecutive bits with the same polarity are detected, the bit stuffing rule has been violated. a stuff bit error occurs and an error frame is generated. the message is repeated. 19.12.6 error states detected errors are made public to all other nodes via error frames. the transmission of the erroneous message is aborted and the frame is repeated as soon as possible. furthermore, each can node is in one of the three error states ?error-active?, ?error-passive? or ?bus-off? according to the value of the internal error counters. the error-active state is the usual state, where the bus node can transmit messages and activate error frames (made of dominant bits) without any restrictions. in the error-passive state, messages and passive error frames (made of recessive bits) may be transmitted. the bus-off state makes it temporarily impossible for the station to participate in the bus communication. during this state, messages can neither be received nor transmitted. 19.12.7 error modes and error counters the pic18fxx8 contains two error counters: the receive error counter (rxerrcnt) and the transmit error counter (txerrcnt). the values of both counters can be read by the mcu. these counters are incremented or decremented in accordance with the can bus specification. the pic18fxx8 is error-active if both error counters are below the error-passive limit of 128. it is error- passive if at least one of the error counters equals or exceeds 128. it goes to bus-off if the transmit error counter equals or exceeds the bus-off limit of 256. the device remains in this state until the bus-off recovery sequence is received. the bus-off recovery sequence consists of 128 occurrences of 11 consecutive recessive bits (see figure 19-10). note that the can module, after going bus-off, will recover back to error- active without any intervention by the mcu if the bus remains idle for 128 x 11 bit times. if this is not desired, the error interrupt service routine should address this. the current error mode of the can module can be read by the mcu via the comstat register. additionally, there is an error state warning flag bit, ewarn, which is set if at least one of the error counters equals or exceeds the error warning limit of 96. ewarn is reset if both error counters are less than the error warning limit. pic18fxx8 ds41159e-page 238 ? 2006 microchip technology inc. figure 19-10: error modes state diagram 19.13 can interrupts the module has several sources of interrupts. each of these interrupts can be individually enabled or disabled. the canintf register contains interrupt flags. the caninte register contains the enables for the 8 main interrupts. a special set of read-only bits in the canstat register, the icode bits, can be used in combination with a jump table for efficient handling of interrupts. all interrupts have one source, with the exception of the error interrupt. any of the error interrupt sources can set the error interrupt flag. the source of the error interrupt can be determined by reading the communication status register, comstat. the interrupts can be broken up into two categories: receive and transmit interrupts. the receive related interrupts are: ? receive interrupts ? wake-up interrupt ? receiver overrun interrupt ? receiver warning interrupt ? receiver error-passive interrupt the transmit related interrupts are: ? transmit interrupts ? transmitter warning interrupt ? transmitter error-passive interrupt ? bus-off interrupt 19.13.1 interrupt code bits the source of a pending interrupt is indicated in the icode (interrupt code) bits of the canstat register (icode<2:0>). interrupts are internally prioritized such that the higher priority interrupts are assigned lower icode values. once the highest priority interrupt con- dition has been cleared, the code for the next highest priority interrupt that is pending (if any) will be reflected by the icode bits (see table 19-3, following page). note that only those interrupt sources that have their associated caninte enable bit set will be reflected in the icode bits. 19.13.2 transmit interrupt when the transmit interrupt is enabled, an interrupt will be generated when the associated transmit buffer becomes empty and is ready to be loaded with a new message. the txbnif bit will be set to indicate the source of the interrupt. the interrupt is cleared by the mcu resetting the txbnif bit to a ? 0 ?. 19.13.3 receive interrupt when the receive interrupt is enabled, an interrupt will be generated when a message has been successfully received and loaded into the associated receive buffer. this interrupt is activated immediately after receiving the eof field. the rxbnif bit will be set to indicate the source of the interrupt. the interrupt is cleared by the mcu resetting the rxbnif bit to a ? 0 ?. bus- off error- active error- passive rxerrcnt < 127 or txerrcnt < 127 rxerrcnt > 127 or txerrcnt > 127 txerrcnt > 255 128 occurrences of 11 consecutive ?recessive? bits reset ? 2006 microchip technology inc. ds41159e-page 239 pic18fxx8 table 19-3: values for icode<2:0> 19.13.4 message error interrupt when an error occurs during transmission or reception of a message, the message error flag irxif will be set and if the irxie bit is set, an interrupt will be generated. this is intended to be used to facilitate baud rate determination when used in conjunction with listen only mode. 19.13.5 bus activity wake-up interrupt when the pic18fxx8 is in sleep mode and the bus activity wake-up interrupt is enabled, an interrupt will be generated and the wakif bit will be set when activity is detected on the can bus. this interrupt causes the pic18fxx8 to exit sleep mode. the interrupt is reset by the mcu, clearing the wakif bit. 19.13.6 error interrupt when the error interrupt is enabled, an interrupt is generated if an overflow condition occurs or if the error state of transmitter or receiver has changed. the error flags in comstat will indicate one of the following conditions. 19.13.6.1 receiver overflow an overflow condition occurs when the mab has assembled a valid received message (the message meets the criteria of the acceptance filters) and the receive buffer associated with the filter is not available for loading of a new message. the associated comstat.rxnovfl bit will be set to indicate the overflow condition. this bit must be cleared by the mcu. 19.13.6.2 receiver warning the receive error counter has reached the mcu warning limit of 96. 19.13.6.3 transmitter warning the transmit error counter has reached the mcu warning limit of 96. 19.13.6.4 receiver bus passive the receive error counter has exceeded the error- passive limit of 127 and the device has gone to error-passive state. 19.13.6.5 transmitter bus passive the transmit error counter has exceeded the error- passive limit of 127 and the device has gone to error-passive state. 19.13.6.6 bus-off the transmit error counter has exceeded 255 and the device has gone to bus-off state. 19.13.7 interrupt acknowledge interrupts are directly associated with one or more status flags in the pir register. interrupts are pending as long as one of the flags is set. once an interrupt flag is set by the device, the flag cannot be reset by the microcontroller until the interrupt condition is removed. icod <2:0> interrupt boolean expression 000 none err ?wak ?tx0 ?tx1 ?tx2 ?rx0 ? rx1 001 error err 010 txb2 err ?tx0 ?tx1 ?tx2 011 txb1 err ?tx0 ?tx1 100 txb0 err ?tx0 101 rxb1 err ?tx0 ?tx1 ?tx2 ?rx0 ?rx1 110 rxb0 err ?tx0 ?tx1 ?tx2 ?rx0 111 wake on interrupt err ?tx0 ?tx1 ?tx2 ?rx0 ?rx1 ? wak key: err = errif * errie rx0 = rxb0if * rxb0ie tx0 = txb0if * txb0ie rx1 = rxb1if * rxb1ie tx1 = txb1if * txb1ie wak = wakif * wakie tx2 = txb2if * txb2ie pic18fxx8 ds41159e-page 240 ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. ds41159e-page 241 pic18fxx8 20.0 compatible 10-bit analog- to-digital converter (a/d) module the analog-to-digital (a/d) converter module has five inputs for the pic18f2x8 devices and eight for the pic18f4x8 devices. this module has the adcon0 and adcon1 register definitions that are compatible with the picmicro ? mid-range a/d module. the a/d allows conversion of an analog input signal to a corresponding 10-bit digital number. the a/d module has four regi sters. these registers are: ? a/d result high register (adresh) ? a/d result low register (adresl) ? a/d control register 0 (adcon0) ? a/d control register 1 (adcon1) the adcon0 register, shown in register 20-1, controls the operation of the a/d module. the adcon1 register, shown in register 20-2, configures the functions of the port pins. register 20-1: adcon0: a/d control register 0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done ?adon bit 7 bit 0 bit 7-6 adcs1:adcs0: a/d conversion clock select bits (adcon0 bits in bold ) bit 5-3 chs2:chs0: analog channel select bits 000 = channel 0 (an0) 001 = channel 1 (an1) 010 = channel 2 (an2) 011 = channel 3 (an3) 100 = channel 4 (an4) 101 = channel 5 (an5) (1) 110 = channel 6 (an6) (1) 111 = channel 7 (an7) (1) note 1: these channels are unimplemented on pic18f2x8 (28-pin) devices. do not select any unimplemented channel. bit 2 go/done : a/d conversion status bit when adon = 1 : 1 = a/d conversion in progress (setting this bit starts the a/d conversion which is automatically cleared by hardware when the a/d conversion is complete) 0 = a/d conversion not in progress bit 1 unimplemented: read as ? 0 ? bit 0 adon: a/d on bit 1 = a/d converter module is powered up 0 = a/d converter module is shut-off and consumes no operating current legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown adcon1 pic18fxx8 ds41159e-page 242 ? 2006 microchip technology inc. register 20-2: adcon1: a/d control register 1 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm adcs2 ? ? pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 bit 7 adfm: a/d result format select bit 1 = right justified. six (6) most significant bits of adresh are read as ? 0 ?. 0 = left justified. six (6) least significant bits of adresl are read as ? 0 ?. bit 6 adcs2: a/d conversion clock select bit (adcon1 bits in bold ) bit 5-4 unimplemented: read as ? 0 ? bit 3-0 pcfg3:pcfg0: a/d port configuration control bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: on any device reset, the port pins that are multiplexed with analog functions (anx) are forced to be analog inputs. adcon1 ? 2006 microchip technology inc. ds41159e-page 243 pic18fxx8 the analog reference voltage is software selectable to either the device?s positive and negative supply voltage (v dd and v ss ) or the voltage level on the ra3/an3/ v ref + pin and ra2/an2/v ref - pin. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/d?s internal rc oscillator. the output of the sample and hold is the input into the converter which generates the result via successive approximation. a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion is aborted. each port pin associated with the a/d converter can be configured as an analog input (ra3 can also be a voltage reference) or as a digital i/o. the adresh and adresl registers contain the result of the a/d conversion. when the a/d conversion is com- plete, the result is loaded into the adresh/adresl registers, the go/done bit (adcon0<2>) is cleared and a/d interrupt flag bit, adif, is set. the block diagram of the a/d module is shown in figure 20-1. figure 20-1: a/d block diagram (input voltage) v ain v ref + reference voltage v dd pcfg0 chs2:chs0 an7 (1) an6 (1) an5 (1) an4 an3 an2 an1 an0 111 110 101 100 011 010 001 000 10-bit converter v ref - v ss a/d note 1: channels an5 through an7 are not available on pic18f2x8 devices. 2: all i/o pins have diode protection to v dd and v ss . pic18fxx8 ds41159e-page 244 ? 2006 microchip technology inc. the value that is in the adresh/adresl registers is not modified for a power-on reset. the adresh/ adresl registers will contain unknown data after a power-on reset. after the a/d module has been configured as desired, the selected channel must be acquired before the conversion is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 20.1 ?a/d acquisition requirements? . after this acquisi- tion time has elapsed, the a/d conversion can be started. the following steps should be followed for doing an a/d conversion: 1. configure the a/d module: ? configure analog pins, voltage reference and digital i/o (adcon1) ? select a/d input channel (adcon0) ? select a/d conversion clock (adcon0) ? turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): ? clear adif bit ? set adie bit ?set gie bit 3. wait the required acquisition time. 4. start conversion: ? set go/done bit (adcon0) 5. wait for a/d conversion to complete, by either: ? polling for the go/done bit to be cleared or ? waiting for the a/d interrupt 6. read a/d result registers (adresh/adresl); clear bit adif if required. 7. for next conversion, go to step 1 or step 2 as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before next acquisition starts. 20.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 20-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for analog sources is 2.5 k . after the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. figure 20-2: analog input model note: when the conversion is started, the holding capacitor is disconnected from the input pin. v ain c pin rs anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = 120 pf v ss 6v sampling switch 5v 4v 3v 2v 567891011 (k ) v dd 500 na legend :c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions ? 2006 microchip technology inc. ds41159e-page 245 pic18fxx8 to calculate the minimum acquisition time, equation 20-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. example 20-1 shows the calculation of the minimum required acquisition time t acq . this calculation is based on the following application system assumptions: ?c hold = 120 pf ? rs = 2.5 k ? conversion error 1/2 lsb ?v dd = 5v rss = 7 k ? temperature = 50 c (system max.) ?v hold =0v @ time = 0 equation 20-1: a cquisition time equation 20-2: a/d minimum charging time example 20-1: calculating the minimum required acquisition time t acq = amplifier settling time + holding capacitor charging time + temperature coefficient =t amp + t c + t coff v hold = (v ref ? (v ref /2048)) ? (1 ? e (-tc/c hold (r ic + r ss + r s )) ) or tc = -(120 pf)(1 k + r ss + r s ) ln(1/2047) t acq =t amp + t c + t coff temperature coefficient is only required for temperatures > 25 c. t acq =2 s + t c + [(temp ? 25 c)(0.05 s/ c)] t c =-c hold (r ic + r ss + r s ) ln(1/2047) -120 pf (1 k + 7 k + 2.5 k ) ln(0.0004885) -120 pf (10.5 k ) ln(0.0004885) -1.26 s (-7.6241) 9.61 s t acq =2 s + 9.61 s + [(50 c ? 25 c)(0.05 s/ c)] 11.61 s + 1.25 s 12.86 s note: when using external voltage references with the a/d converter, the source impedance of the external voltage references must be less than 20 to obtain the specified a/d resolution. higher reference source impedances will increase both offset and gain errors. resistive voltage dividers will not provide a sufficiently low source impedance. to maintain the best possible performance in a/d conversions, external v ref inputs should be buffered with an operational amplifier or other low output impedance circuit. pic18fxx8 ds41159e-page 246 ? 2006 microchip technology inc. 20.2 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 12 t ad per 10-bit conversion. the source of the a/d conversion clock is software selectable. the seven possible options for t ad are: ?2 t osc ?4 t osc ?8 t osc ?16 t osc ?32 t osc ?64 t osc ? internal rc oscillator. for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 s. table 20-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. 20.3 configuring analog port pins the adcon1, trisa and trise registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs2:chs0 bits and the tris bits. table 20-1: t ad vs. device operating frequencies table 20-2: t ad vs. device operating frequencies (for extended, lf devices) note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs will convert an analog input. analog levels on a digitally configured input will not affect the conversion accuracy. 2: analog levels on any pin that is defined as a digital input (including the an4:an0 pins) may cause the input buffer to consume current that is out of the device?s specification. ad clock source (t ad ) device frequency operation adcs2:adcs0 20 mhz 5 mhz 1.25 mhz 333.33 khz 2 t osc 000 100 ns (2) 400 ns (2) 1.6 s6 s 4 t osc 100 200 ns (2) 800 ns (2) 3.2 s12 s 8 t osc 001 400 ns (2) 1.6 s6.4 s 24 s (3) 16 t osc 101 800 ns (2) 3.2 s 12.8 s 48 s (3) 32 t osc 010 1.6 s6.4 s 25.6 s (3) 96 s (3) 64 t osc 110 3.2 s12.8 s 51.2 s (3) 192 s (3) rc 011 2-6 s (1) 2-6 s (1) 2-6 s (1) 2-6 s (1) legend: shaded cells are outside of recommended range. note 1: the rc source has a typical t ad time of 4 s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. ad clock source (t ad ) device frequency operation adcs2:adcs0 4 mhz 2 mhz 1.25 mhz 333.33 khz 2 t osc 000 500 ns (2) 1.0 s (2) 1.6 s (2) 6 s 4 t osc 100 1.0 s (2) 2.0 s (2) 3.2 s (2) 12 s 8 t osc 001 2.0 s (2) 4.0 s6.4 s 24 s (3) 16 t osc 101 4.0 s (2) 8.0 s 12.8 s 48 s (3) 32 t osc 010 8.0 s16.0 s 25.6 s (3) 96 s (3) 64 t osc 110 16.0 s32.0 s 51.2 s (3) 192 s (3) rc 011 3-9 s (1) 3-9 s (1) 3-9 s (1) 3-9 s (1) legend: shaded cells are outside of recommended range. note 1: the rc source has a typical t ad time of 6 s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. ? 2006 microchip technology inc. ds41159e-page 247 pic18fxx8 20.4 a/d conversions figure 20-4 shows the operation of the a/d converter after the go bit has been set. clearing the go/done bit during a conversion will abort the current conver- sion. the a/d result register pair will not be updated with the partially completed a/d conversion sample. that is, the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is aborted, a 2 t ad wait is required before the next acquisition is started. after this 2 t ad wait, acquisition on the selected channel is automatically started. 20.4.1 a/d result registers the adresh:adresl register pair is the location where the 10-bit a/d result is loaded at the completion of the a/d conversion. this register pair is 16 bits wide. the a/d module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register. the a/d format select bit (adfm) controls this justification. figure 20-3 shows the operation of the a/d result justi- fication. the extra bits are loaded with ? 0 ?s. when an a/d result will not overwrite these locations (a/d disable), these registers may be used as two general purpose 8-bit registers. figure 20-3: a/d result justification note: the go/done bit should not be set in the same instruction that turns on the a/d. 10-bit result adresh adresl 0000 00 adfm = 0 0 2 1 0 7 7 10-bit result adresh adresl 10-bit result 0000 00 7 0 7 6 5 0 adfm = 1 right justified left justified pic18fxx8 ds41159e-page 248 ? 2006 microchip technology inc. 20.5 use of the eccp trigger an a/d conversion can be started by the ?special event trigger? of the eccp module. this requires that the eccp1m3:eccp1m0 bits (eccp1con<3:0>) be pro- grammed as ? 1011 ? and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/ done bit will be set, starting the a/d conversion and the timer1 (or timer3) counter will be reset to zero. timer1 (or timer3) is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving adresh/adresl to the desired location). the appropriate analog input channel must be selected and the minimum acquisition done before the ?special event trigger? sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), the ?special event trigger? will be ignored by the a/d module but will still reset the timer1 (or timer3) counter. figure 20-4: a/d conversion t ad cycles table 20-3: summary of a/d registers t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go bit holding capacitor is disconnected from analog input b9 b8 b7 b6 b5 b4 b3 b2 t ad 9 t ad 10 b1 b0 t cy - t ad next q4: adresh/adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0 (typically 100 ns) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 pir2 ?cmif (1) ?eeif bclif lvdif tmr3if eccp1if (1) -0-0 0000 -0-0 0000 pie2 ?cmie (1) ?eeie bclie lvdie tmr3ie eccp1ie (1) -0-0 0000 -0-0 0000 ipr2 ?cmip (1) ?eeip bclip lvdip tmr3ip eccp1ip (1) -1-1 1111 -1-1 1111 adresh a/d result register xxxx xxxx uuuu uuuu adresl a/d result register xxxx xxxx uuuu uuuu adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done ?adon 0000 00-0 0000 00-0 adcon1 adfm adcs2 ? ? pcfg3 pcfg2 pcfg1 pcfg0 00-- 0000 00-- 0000 porta ? ra6 ra5 ra4 ra3 ra2 ra1 ra0 -x0x 0000 -u0u 0000 trisa ? porta data direction register -111 1111 -111 1111 porte ? ? ? ? ? re2 re1 re0 ---- -xxx ---- -000 late ? ? ? ? ? late2 late1 late0 ---- -xxx ---- -uuu trise ibf obf ibov pspmode ? trise2 trise1 trise0 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used for a/d conversion. note 1: these bits are reserved on pic18f2x8 devices; always maintain these bits clear. ? 2006 microchip technology inc. ds41159e-page 249 pic18fxx8 21.0 comparator module the comparator module contains two analog com- parators. the inputs to the comparators are multiplexed with the rd0 through rd3 pins. the on-chip voltage reference ( section 22.0 ?comparator voltage reference module? ) can also be an input to the comparators. the cmcon register, shown in register 21-1, controls the comparator input and output multiplexers. a block diagram of the comparator is shown in figure 21-1. register 21-1: cmcon: comp arator control register note: the analog comparators are only available on the pic18f448 and pic18f458. r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 c2out c1out c2inv c1inv cis cm2 cm1 cm0 bit 7 bit 0 bit 7 c2out : comparator 2 output bit when c2inv = 0 : 1 = c2 v in + > c2 v in - 0 = c2 v in + < c2 v in - when c2inv = 1 : 1 = c2 v in + < c2 v in - 0 = c2 v in + > c2 v in - bit 6 c1out : comparator 1 output bit when c1inv = 0 : 1 = c1 v in + > c1 v in - 0 = c1 v in + < c1 v in - when c1inv = 1 : 1 = c1 v in + < c1 v in - 0 = c1 v in + > c1 v in - bit 5 c2inv : comparator 2 output inversion bit 1 = c2 output inverted 0 = c2 output not inverted bit 4 c1inv : comparator 1 output inversion bit 1 = c1 output inverted 0 = c1 output not inverted bit 3 cis : comparator input switch bit when cm2:cm0 = 110 : 1 =c1 v in - connects to rd0/psp0 c2 v in - connects to rd2/psp2 0 =c1 v in - connects to rd1/psp1 c2 v in - connects to rd3/psp3 bit 2-0 cm2:cm0 : comparator mode bits figure 21-1 shows the comparator modes and cm2:cm0 bit settings. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 250 ? 2006 microchip technology inc. 21.1 comparator configuration there are eight modes of operation for the compara- tors. the cmcon register is used to select these modes. figure 21-1 shows the eight possible modes. the trisd register controls the data direction of the comparator pins for each mode. if the comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in section 27.0 ?electrical characteristics? . figure 21-1: comparator i/o operating modes note: comparator interrupts should be disabled during a comparator mode change; otherwise, a false interrupt may occur. c1 rd1/psp1 v in - v in + off (read as ? 0 ?) comparators reset (por default value) a a cm2:cm0 = 000 c2 rd3/psp3 v in - v in + rd2/psp2 off (read as ? 0 ?) a a c1 rd1/psp1 v in - v in + rd0/psp0 c1out two independent comparators a a cm2:cm0 = 010 c2 rd3/psp3 v in - v in + rd2/psp2 c2out a a c1 rd1/psp1 v in - v in + rd0/psp0 c1out two common reference comparators a a cm2:cm0 = 100 c2 rd3/psp3 v in - v in + rd2/psp2 c2out a d c2 rd3/psp3 v in - v in + rd2/psp2 off (read as ? 0 ?) one independent comparator with output d d cm2:cm0 = 001 c1 rd1/psp1 v in - v in + rd0/psp0 c1out a a c1 rd1/psp1 v in - v in + rd0/psp0 off (read as ? 0 ?) comparators off d d cm2:cm0 = 111 c2 rd3/psp3 v in - v in + rd2/psp2 off (read as ? 0 ?) d d c1 rd1/psp1 v in - v in + rd0/psp0 c1out four inputs multiplexed to two comparators a a cm2:cm0 = 110 c2 rd3/psp3 v in - v in + rd2/psp2 c2out a a from v ref module cis = 0 cis = 1 cis = 0 cis = 1 c1 rd1/psp1 v in - v in + rd0/psp0 c1out two common reference comparators with outputs a a cm2:cm0 = 101 c2 rd3/psp3 v in - v in + rd2/psp2 c2out a d a = analog input, port reads zeros always d = digital input cis (cmcon<3>) is the comparator input switch cv ref c1 rd1/psp1 v in - v in + rd0/psp0 c1out two independent comparators with outputs a a cm2:cm0 = 011 c2 rd3/psp3 v in - v in + rd2/psp2 c2out a a re1/an6/wr /c1out re2/an7/cs /c2out re1/an6/wr / re2/an7/cs /c2out re1/an6/wr /c1out rd0/psp0 c1out ? 2006 microchip technology inc. ds41159e-page 251 pic18fxx8 21.2 comparator operation a single comparator is shown in figure 21-2 along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in -, the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in -, the output of the comparator is a digital high level. the shaded areas of the output of the comparator in figure 21-2 represent the uncertainty due to input offsets and response time. 21.3 comparator reference an external or internal reference signal may be used depending on the comparator operating mode. the analog signal present at v in - is compared to the signal at v in + and the digital output of the comparator is adjusted accordingly (figure 21-2). figure 21-2: single comparator 21.3.1 external reference signal when external voltage references are used, the comparator module can be configured to have the com- parators operate from the same or different reference sources. however, threshold detector applications may require the same reference. the reference signal must be between v ss and v dd and can be applied to either pin of the comparator(s). 21.3.2 internal reference signal the comparator module also allows the selection of an internally generated voltage reference for the compara- tors. section 22.0 ?comparator voltage reference module? contains a detailed description of the module that provides this signal. the internal reference signal is used when comparators are in mode cm<2:0> = 110 (figure 21-1). in this mode, the internal voltage reference is applied to the v in + pin of both comparators. 21.4 comparator response time response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. if the internal ref- erence is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. otherwise, the maximum delay of the comparators should be used ( section 27.0 ?electrical characteristics? ). 21.5 comparator outputs the comparator outputs are read through the cmcon register. these bits are read-only. the comparator outputs may also be directly output to the re1 and re2 i/o pins. when enabled, multiplexors in the output path of the re1 and re2 pins will switch and the output of each pin will be the unsynchronized output of the comparator. the uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. figure 21-3 shows the comparator output block diagram. the trise bits will still function as an output enable/ disable for the re1 and re2 pins while in this mode. the polarity of the comparator outputs can be changed using the c2inv and c1inv bits (cmcon<4:5>). - + v in + v in - output v in? v in+ output output v in + v in - note 1: when reading the port register, all pins configured as analog inputs will read as a ? 0 ?. pins configured as digital inputs will convert an analog input according to the schmitt trigger input specification. 2: analog levels on any pin defined as a dig- ital input may cause the input buffer to consume more current than is specified. pic18fxx8 ds41159e-page 252 ? 2006 microchip technology inc. figure 21-3: comparator output block diagram 21.6 comparator interrupts the comparator interrupt flag is set whenever there is a change in the output value of either comparator. software will need to maintain information about the status of the output bits, as read from cmcon<7:6>, to determine the actual change that occurred. the cmif bit (pir2 register) is the comparator interrupt flag. the cmif bit must be reset by clearing ? 0 ?. since it is also possible to write a ? 1 ? to this register, a simulated interrupt may be initiated. the cmie bit (pie2 register) and the peie bit (intcon register) must be set to enable the interrupt. in addition, the gie bit must also be set. if any of these bits are clear, the interrupt is not enabled, though the cmif bit will still be set if an interrupt condition occurs. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of cmcon will end the mismatch condition. b) clear flag bit cmif. a mismatch condition will continue to set flag bit cmif. reading cmcon will end the mismatch condition and allow flag bit cmif to be cleared. d q en to re1 or re2 pin bus data read cmcon set multiplex cmif bit - + d q en cl port pins read cmcon reset from other comparator cxinv note: if a change in the cmcon register (c1out or c2out) should occur when a read operation is being executed (start of the q2 cycle), then the cmif (pir2 register) interrupt flag may not get set. ? 2006 microchip technology inc. ds41159e-page 253 pic18fxx8 21.7 comparator operation during sleep when a comparator is active and the device is placed in sleep mode, the comparator remains active and the interrupt is functional if enabled. this interrupt will wake-up the device from sleep mode when enabled. while the comparator is powered up, higher sleep currents than shown in the power-down current specification will occur. each operational comparator will consume additional current, as shown in the com- parator specifications. to minimize power consumption while in sleep mode, turn off the comparators, cm<2:0> = 111 , before entering sleep. if the device wakes up from sleep, the contents of the cmcon register are not affected. 21.8 effects of a reset a device reset forces the cmcon register to its reset state, causing the comparator module to be in the comparator reset mode, cm<2:0> = 000 . this ensures that all potential inputs are analog inputs. device current is minimized when analog inputs are present at reset time. the comparators will be powered down during the reset interval. 21.9 analog input connection considerations a simplified circuit for an analog input is shown in figure 21-4. since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up condition may occur. a maximum source impedance of 10 k is recommended for the analog sources. any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. figure 21-4: analog input model va r s < 10k a in c pin 5 pf v dd v t = 0.6v v t = 0.6v r ic i leakage 500 na v ss legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance va = analog voltage pic18fxx8 ds41159e-page 254 ? 2006 microchip technology inc. table 21-1: registers associated with comparator module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0000 0000 0000 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 0000 0000 0000 0000 intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir2 ?cmif (1) ? eeif bclif lvdif tmr3if eccp1if (1) -0-0 0000 -0-0 0000 pie2 ?cmie (1) ? eeie bclie lvdie tmr3ie eccp1ie (1) -0-0 0000 -0-0 0000 ipr2 ?cmip (1) ? eeip bclip lvdip tmr3ip eccp1ip (1) -1-1 1111 -1-1 1111 portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu latd latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 xxxx xxxx uuuu uuuu trisd portd data direction register 1111 1111 1111 1111 porte ? ? ? ? ?re2re1 re0 ---- -xxx ---- -000 late ? ? ? ? ?late2late1 late0 ---- -xxx ---- -uuu trise ibf (1) obf (1) ibov (1) pspmode (1) ? trise2 trise1 trise0 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ? note 1: these bits are reserved on pic18f2x8 devices; always maintain these bits clear. ? 2006 microchip technology inc. ds41159e-page 255 pic18fxx8 22.0 comparator voltage reference module this module is a 16-tap resistor ladder network that provides a selectable voltage reference. the resistor ladder is segmented to provide two ranges of cv ref values and has a power-down function to conserve power when the reference is not being used. the cvrcon register controls the operation of the reference, as shown in register 22-1. the block diagram is shown in figure 22-1. the comparator and reference supply voltage can come from either v dd and v ss , or the external v ref + and v ref -, that are multiplexed with ra3 and ra2. the comparator reference supply voltage is controlled by the cvrss bit. 22.1 configuring the comparator voltage reference the comparator voltage reference can output 16 distinct voltage levels for each range. the equations used to calculate the output of the comparator voltage reference are as follows. equation 22-1: equation 22-2: the settling time of the comparator voltage reference must be considered when changing the ra0/an0/ cv ref output (see table 27-4 in section 27.2 ?dc characteristics? ). register 22-1: cvrcon: comparator vo ltage reference control register note: the comparator voltage reference is only available on the pic18f448 and pic18f458. if cvrr = 1: cv ref = (cvr<3:0>/24) x cv rsrc where: cvrss = 1, cv rsrc = (v ref +) ? (v ref -) cvrss = 0, cv rsrc = av dd ? av ss if cvrr = 0: cv ref = (cv rsrc x 1/4) + (cvr<3:0>/32) x cv rsrc where: cvrss = 1, cv rsrc = (v ref +) ? (v ref -) cvrss = 0, cv rsrc = av dd ? av ss r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 bit 7 bit 0 bit 7 cvren : comparator voltage reference enable bit 1 =cv ref circuit powered on 0 =cv ref circuit powered down bit 6 cvroe : comparator v ref output enable bit 1 =cv ref voltage level is also output on the ra0/an0/cv ref pin 0 =cv ref voltage is disconnected from the ra0/an0/cv ref pin bit 5 cvrr : comparator v ref range selection bit 1 =0.00 cv rsrc to 0.625 cv rsrc with cv rsrc /24 step size 0 =0.25 cv rsrc to 0.719 cv rsrc with cv rsrc /32 step size bit 4 cvrss : comparator v ref source selection bit 1 = comparator reference source, cv rsrc = (v ref +) ? (v ref -) 0 = comparator reference source, cv rsrc = v dd ? v ss bit 3-0 cvr<3:0>: comparator v ref value selection 0 cvr3:cvr0 15 bits when cvrr = 1 : cv ref = (cvr3:cvr0/24) ? (cv rsrc ) when cvrr = 0 : cv ref = 1/4 ? (cv rsrc ) + (cvr3:cvr0/32) ? (cv rsrc ) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 256 ? 2006 microchip technology inc. figure 22-1: voltage reference block diagram 22.2 voltage reference accuracy/error the full range of voltage reference cannot be realized due to the construction of the module. the transistors on the top and bottom of the resistor ladder network (figure 22-1) keep v ref from approaching the refer- ence source rails. the voltage reference is derived from the reference source; therefore, the v ref output changes with fluctuations in that source. the absolute accuracy of the voltage reference can be found in section 27.0 ?electrical characteristics? . 22.3 operation during sleep when the device wakes up from sleep through an interrupt or a watchdog timer time-out, the contents of the cvrcon register are not affected. to minimize current consumption in sleep mode, the voltage reference should be disabled. 22.4 effects of a reset a device reset disables the voltage reference by clearing bit cvren (cvrcon register). this reset also disconnects the reference from the ra2 pin by clearing bit cvroe (cvrcon register) and selects the high-voltage range by clearing bit cvrr (cvrcon register). the cvrss value select bits, cvrcon<3:0>, are also cleared. 22.5 connection considerations the voltage reference module operates independently of the comparator module. the output of the reference generator may be connected to the ra0/an0 pin if the trisa<0> bit is set and the cvroe bit (cvrcon<6>) is set. enabling the voltage reference output onto the ra0/an0 pin, with an input signal present, will increase current consumption. connecting ra0/an0 as a digital output, with cvrss enabled, will also increase current consumption. the ra0/an0 pin can be used as a simple d/a output with limited drive capability. due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to v ref . figure 22-2 shows an example buffering technique. cvrr 8r cvr3 cvr0 (from cvrcon<3:0>) 16-to-1 analog mux 8r r r r r ra0/an0/cv ref 16 stages cvrss = 1 v dd v ref + cvrss = 1 cvrss = 0 ra2/an2/v ref - cvrss = 0 or cv ref of comparator cvren ? 2006 microchip technology inc. ds41159e-page 257 pic18fxx8 figure 22-2: voltage reference output buffer example table 22-1: registers associated with comparator voltage reference cv ref output + ? ? ? cv ref module voltage reference output impedance r (1) ra0/an0 note 1: r is dependent upon the voltage reference c onfiguration cvrcon<3:0> and cvrcon<5>. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 0000 0000 0000 0000 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0000 0000 0000 trisa ? trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 -111 1111 -111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used with the comparator voltage reference. pic18fxx8 ds41159e-page 258 ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. ds41159e-page 259 pic18fxx8 23.0 low-voltage detect in many applications, the ability to determine if the device voltage (v dd ) is below a specified voltage level is a desirable feature. a window of operation for the application can be created, where the application software can do ?housekeeping tasks? before the device voltage exits the valid operating range. this can be done using the low-voltage detect module. this module is a software programmable circuitry, where a device voltage trip point can be specified. when the voltage of the device becomes lower than the specified point, an interrupt flag is set. if the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to that interrupt source. the low-voltage detect circuitry is completely under software control. this allows the circuitry to be ?turned off? by the software which minimizes the current consumption for the device. figure 23-1 shows a possible application voltage curve (typically for batteries). over time, the device voltage decreases. when the device voltage equals voltage v a , the lvd logic generates an interrupt. this occurs at time t a . the application software then has the time, until the device voltage is no longer in valid operating range, to shutdown the system. voltage point v b is the minimum valid operating voltage specification. this occurs at time t b . the difference t b ? t a is the total time for shutdown. the block diagram for the lvd module is shown in figure 23-2. a comparator uses an internally gener- ated reference voltage as the set point. when the selected tap output of the device voltage crosses the set point (is lower than), the lvdif bit is set. each node in the resistor divider represents a ?trip point? voltage. the ?trip point? voltage is the minimum supply voltage level at which the device can operate before the lvd module asserts an interrupt. when the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module. the comparator then generates an interrupt signal, setting the lvdif bit. this voltage is software programmable to any one of 16 values (see figure 23-2). the trip point is selected by programming the lvdl3:lvdl0 bits (lvdcon<3:0>). figure 23-1: typical low-voltage detect application time voltage v a v b t a t b v a = lvd trip point v b = minimum valid device operating voltage legend: pic18fxx8 ds41159e-page 260 ? 2006 microchip technology inc. figure 23-2: low-voltage detect (lvd) block diagram the lvd module has an additional feature that allows the user to supply the trip voltage to the module from an external source. this mode is enabled when bits lvdl3:lvdl0 are set to ? 1111 ?. in this state, the com- parator input is multiplexed from the external input pin lvdin to one input of the comparator (figure 23-3). the other input is connected to the internally generated voltage reference (parameter #d423 in section 27.2 ?dc characteristics? ). this gives users flexibility, because it allows them to configure the low-voltage detect interrupt to occur at any voltage in the valid operating range. figure 23-3: low-voltage detect (lvd) with external input block diagram lvdif v dd 16-to-1 mux lvden lvdcon internally generated reference voltage, lvdin lvdl3:lvdl0 register 1.2v typical lvd en 16-to-1 mux bgap boden lvden vxen lvdin v dd v dd externally generated trip point lvdl3:lvdl0 lvdcon register ? 2006 microchip technology inc. ds41159e-page 261 pic18fxx8 23.1 control register the low-voltage detect control register controls the operation of the low voltage detect circuitry. register 23-1: lvdcon: low-voltag e detect control register u-0 u-0 r-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 ? ? irvst lvden lvdl3 lvdl2 lvdl1 lvdl0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5 irvst: internal reference voltage stable flag bit 1 = indicates that the low-voltage detect logic will generate the interrupt flag at the specified voltage range 0 = indicates that the low-voltage detect logic will not generate the interrupt flag at the specified voltage range and the lvd interrupt should not be enabled bit 4 lvden: low-voltage detect power enable bit 1 = enables lvd, powers up lvd circuit 0 = disables lvd, powers down lvd circuit bit 3-0 lvdl3:lvdl0: low-voltage detection limit bits 1111 = external analog input is used (input comes from the lvdin pin) 1110 = 4.45v min.-4.83v max. 1101 = 4.16v min.-4.5v max. 1100 = 3.96v min.-4.2v max. 1011 = 3.76v min.-4.08v max. 1010 = 3.57v min.-3.87v max. 1001 = 3.47v min.-3.75v max. 1000 = 3.27v min.-3.55v max. 0111 = 2.98v min.-3.22v max. 0110 = 2.77v min.-3.01v max. 0101 = 2.67v min.-2.89v max. 0100 = 2.48v min.-2.68v max. 0011 = 2.37v min.-2.57v max. 0010 = 2.18v min.-2.36v max. 0001 = 1.98v min.-2.14v max. 0000 = reserved note: lvdl3:lvdl0 modes, which result in a trip point below the valid operating voltage of the device, are not tested. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18fxx8 ds41159e-page 262 ? 2006 microchip technology inc. 23.2 operation depending on the power source for the device voltage, the voltage normally decreases relatively slowly. this means that the lvd module does not need to be constantly operating. to decrease the current require- ments, the lvd circuitry only needs to be enabled for short periods where the voltage is checked. after doing the check, the lvd module may be disabled. each time that the lvd module is enabled, the circuitry requires some time to stabilize. after the circuitry has stabilized, all status flags may be cleared. the module will then indicate the proper state of the system. the following steps are needed to set up the lvd module: 1. write the value to the lvdl3:lvdl0 bits (lvdcon register) which selects the desired lvd trip point. 2. ensure that lvd interrupts are disabled (the lvdie bit is cleared or the gie bit is cleared). 3. enable the lvd module (set the lvden bit in the lvdcon register). 4. wait for the lvd module to stabilize (the irvst bit to become set). 5. clear the lvd interrupt flag, which may have falsely become set, until the lvd module has stabilized (clear the lvdif bit). 6. enable the lvd interrupt (set the lvdie and the gie bits). figure 23-4 shows typical waveforms that the lvd module may be used to detect. figure 23-4: low-voltage detect waveforms v lvd v dd lvdif v lvd v dd enable lvd internally generated t irvst lvdif may not be set enable lvd lvdif lvdif cleared in software lvdif cleared in software lvdif cleared in software, case 1: case 2: lvdif remains set since lvd condition still exists reference stable internally generated reference stable t irvst ? 2006 microchip technology inc. ds41159e-page 263 pic18fxx8 23.2.1 reference voltage set point the internal reference voltage of the lvd module may be used by other internal circuitry (the programmable brown-out reset). if these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low-voltage condition can be reliably detected. this time is invariant of system clock speed. this start-up time is specified in electrical specification parameter #36. the low-voltage interrupt flag will not be enabled until a stable reference voltage is reached. refer to the waveform in figure 23-4. 23.2.2 current consumption when the module is enabled, the lvd comparator and voltage divider are enabled and will consume static cur- rent. the voltage divider can be tapped from multiple places in the resistor array. total current consumption, when enabled, is specified in electrical specification parameter #d022b. 23.3 operation during sleep when enabled, the lvd circuitry continues to operate during sleep. if the device voltage crosses the trip point, the lvdif bit will be set and the device will wake- up from sleep. device execution will continue from the interrupt vector address if interrupts have been globally enabled. 23.4 effects of a reset a device reset forces all registers to their reset state. this forces the lvd module to be turned off. pic18fxx8 ds41159e-page 264 ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. ds41159e-page 265 pic18fxx8 24.0 special features of the cpu there are several features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving operating modes and offer code protection. these are: ? oscillator selection ? reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) ? interrupts ? watchdog timer (wdt) ? sleep ? code protection ? id locations ? in-circuit serial programming all pic18fxx8 devices have a watchdog timer which is permanently enabled via the configuration bits or software controlled. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt) which provides a fixed delay on power-up only, designed to keep the part in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low-current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost while the lp crystal option saves power. a set of configuration bits is used to select various options. 24.1 configuration bits the configuration bits can be programmed (read as ? 0 ?) or left unprogrammed (read as ? 1 ?), to select various device configurations. these bits are mapped starting at program memory location 300000h. the user will note that address 300000h is beyond the user program memory space. in fact, it belongs to the configuration memory space (300000h-3fffffh) which can only be accessed using table reads and table writes. programming the configuration registers is done in a manner similar to programming the flash memory. the eecon1 register wr bit starts a self-timed write to the configuration register. in normal operation mode, a tblwt instruction, with the tblptr pointed to the configuration register, sets up the address and the data for the configuration register write. setting the wr bit starts a long write to the configuration register. the configuration registers are written a byte at a time. to write or erase a configuration cell, a tblwt instruction can write a ? 1 ? or a ? 0 ? into the cell. table 24-1: configuration bits and device ids file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value 300001h config1h ? ? oscsen ? ? fosc2 fosc1 fosc0 --1- -111 300002h config2l ? ? ? ? borv1 borv0 boren pwrten ---- 1111 300003h config2h ? ? ? ? wdtps2 wdtps1 wdtps0 wdten ---- 1111 300006h config4l debug ? ? ? ?lvp ?stvren 1--- -1-1 300008h config5l ? ? ? ?cp3cp2cp1cp0 ---- 1111 300009h config5h cpd cpb ? ? ? ? ? ? 11-- ---- 30000ah config6l ? ? ? ? wrt3 wrt2 wrt1 wrt0 ---- 1111 30000bh config6h wrtd wrtb wrtc ? ? ? ? ? 111- ---- 30000ch config7l ? ? ? ? ebtr3 ebtr2 ebtr1 ebtr0 ---- 1111 30000dh config7h ? ebtrb ? ? ? ? ? ? -1-- ---- 3ffffeh devid1 dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 (1) 3fffffh devid2 dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 0000 1000 legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. shaded cells are unimplemented, read as ? 0 ?. note 1: see register 24-11 for devid1 values. pic18fxx8 ds41159e-page 266 ? 2006 microchip technology inc. register 24-1: config1h: configuration register 1 high (byte address 300001h) register 24-2: config2l: configuration register 2 low (byte address 300002h) u-0 u-0 r/p-1 u-0 u-0 r/p-1 r/p-1 r/p-1 ? ? oscsen ? ? fosc2 fosc1 fosc0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5 oscsen : oscillator system clock switch enable bit 1 = oscillator system clock switch option is disabled (main oscillator is source) 0 = oscillator system clock switch option is enabled (oscillator switching is enabled) bit 4-3 unimplemented: read as ? 0 ? bit 2-0 fosc2:fosc0 : oscillator selection bits 111 = rc oscillator w/osc2 configured as ra6 110 = hs oscillator with pll enabled/clock frequency = (4 x f osc ) 101 = ec oscillator w/osc2 configured as ra6 100 = ec oscillator w/osc2 configured as divide-by-4 clock output 011 = rc oscillator 010 = hs oscillator 001 = xt oscillator 000 = lp oscillator legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state u-0 u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ? borv1 borv0 boren pwrten bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3-2 borv1:borv0: brown-out reset voltage bits 11 = v bor set to 2.0v 10 = v bor set to 2.7v 01 = v bor set to 4.2v 00 = v bor set to 4.5v bit 1 boren: brown-out reset enable bit 1 = brown-out reset enabled 0 = brown-out reset disabled bit 0 pwrten : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state ? 2006 microchip technology inc. ds41159e-page 267 pic18fxx8 register 24-3: config2h: configuration register 2 high (byte address 300003h) register 24-4: config4l: config uration register 4 low (byte address 300006h) u-0 u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ? wdtps2 wdtps1 wdtps0 wdten bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3-1 wdtps2:wdtps0: watchdog timer postscale select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 note: the watchdog timer postscale select bits configuration used in the pic18fxxx devices has changed from the configuration used in the pic18cxxx devices. bit 0 wdten: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on the swdten bit) legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state r/p-1 u-0 u-0 u-0 u-0 r/p-1 u-0 r/p-1 debug ? ? ? ?lvp ?stvren bit 7 bit 0 bit 7 debug : background debugger enable bit 1 = background debugger disabled. rb6 and rb7 configured as general purpose i/o pins. 0 = background debugger enabled. rb6 and rb7 are dedicated to in-circuit debug. bit 6-3 unimplemented: read as ? 0 ? bit 2 lvp: low-voltage icsp enable bit 1 = low-voltage icsp enabled 0 = low-voltage icsp disabled bit 1 unimplemented: read as ? 0 ? bit 0 stvren: stack full/underflow reset enable bit 1 = stack full/underflow will cause reset 0 = stack full/underflow will not cause reset legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state pic18fxx8 ds41159e-page 268 ? 2006 microchip technology inc. register 24-5: config5l: configuration register 5 low (byte address 300008h) register 24-6: config5h: configuration register 5 high (byte address 300009h) u-0 u-0 u-0 u-0 r/c-1 r/c-1 r/c-1 r/c-1 ? ? ? ?cp3 (1) cp2 (1) cp1 cp0 bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3 cp3: code protection bit (1) 1 = block 3 (006000-007fffh) not code-protected 0 = block 3 (006000-007fffh) code-protected bit 2 cp2: code protection bit (1) 1 = block 2 (004000-005fffh) not code-protected 0 = block 2 (004000-005fffh) code-protected bit 1 cp1: code protection bit 1 = block 1 (002000-003fffh) not code-protected 0 = block 1 (002000-003fffh) code-protected bit 0 cp0: code protection bit 1 = block 0 (000200-001fffh) not code-protected 0 = block 0 (000200-001fffh) code-protected note 1: unimplemented in pic18fx48 devices; maintain this bit set. legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state r/c-1 r/c-1 u-0 u-0 u-0 u-0 u-0 u-0 cpd cpb ? ? ? ? ? ? bit 7 bit 0 bit 7 cpd: data eeprom code protection bit 1 = data eeprom not code-protected 0 = data eeprom code-protected bit 6 cpb: boot block code protection bit 1 = boot block (000000-0001ffh) not code-protected 0 = boot block (000000-0001ffh) code-protected bit 5-0 unimplemented: read as ? 0 ? legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state ? 2006 microchip technology inc. ds41159e-page 269 pic18fxx8 register 24-7: config6l: configuration register 6 low (byte address 30000ah) register 24-8: config6h: co nfiguration register 6 high (byte address 30000bh) u-0 u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ?wrt3 (1) wrt2 (1) wrt1 wrt0 bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3 wrt3: write protection bit (1) 1 = block 3 (006000-007fffh) not write-protected 0 = block 3 (006000-007fffh) write-protected bit 2 wrt2: write protection bit (1) 1 = block 2 (004000-005fffh) not write-protected 0 = block 2 (004000-005fffh) write-protected bit 1 wrt1: write protection bit 1 = block 1 (002000-003fffh) not write-protected 0 = block 1 (002000-003fffh) write-protected bit 0 wrt0: write protection bit 1 = block 0 (000200-001fffh) not write-protected 0 = block 0 (000200-001fffh) write-protected note 1: unimplemented in pic18fx48 devices; maintain this bit set. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state r/p-1 r/p-1 r-1 u-0 u-0 u-0 u-0 u-0 wrtd wrtb wrtc ? ? ? ? ? bit 7 bit 0 bit 7 wrtd: data eeprom write protection bit 1 = data eeprom not write-protected 0 = data eeprom write-protected bit 6 wrtb: boot block write protection bit 1 = boot block (000000-0001ffh) not write-protected 0 = boot block (000000-0001ffh) write-protected bit 5 wrtc: configuration register write protection bit 1 = configuration registers (300000-3000ffh) not write-protected 0 = configuration registers (300000-3000ffh) write-protected note: this bit is read-only and cannot be changed in user mode. bit 4-0 unimplemented: read as ? 0 ? legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state pic18fxx8 ds41159e-page 270 ? 2006 microchip technology inc. register 24-9: config7l: configuration register 7 low (byte address 30000ch) register 24-10: config7h: config uration register 7 high (byte address 30000dh) u-0 u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ? ebtr3 (1) ebtr2 (1) ebtr1 ebtr0 bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3 ebtr3: table read protection bit (1) 1 = block 3 (006000-007fffh) not protected from table reads executed in other blocks 0 = block 3 (006000-007fffh) protected from table reads executed in other blocks bit 2 ebtr2: table read protection bit (1) 1 = block 2 (004000-005fffh) not protected from table reads executed in other blocks 0 = block 2 (004000-005fffh) protected from table reads executed in other blocks bit 1 ebtr1: table read protection bit 1 = block 1 (002000-003fffh) not protected from table reads executed in other blocks 0 = block 1 (002000-003fffh) protected from table reads executed in other blocks bit 0 ebtr0: table read protection bit 1 = block 0 (000200-001fffh) not protected from table reads executed in other blocks 0 = block 0 (000200-001fffh) protected from table reads executed in other blocks note 1: unimplemented in pic18fx48 devices; maintain this bit set. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state u-0 r/p-1 u-0 u-0 u-0 u-0 u-0 u-0 ? ebtrb ? ? ? ? ? ? bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 ebtrb: boot block table read protection bit 1 = boot block (000000-0001ffh) not protected from table reads executed in other blocks 0 = boot block (000000-0001ffh) protected from table reads executed in other blocks bit 5-0 unimplemented: read as ? 0 ? legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state ? 2006 microchip technology inc. ds41159e-page 271 pic18fxx8 register 24-11: devid1: device id register 1 for pic18fxx8 devices (byte address 3ffffeh) register 24-12: devid2: device id register 2 for pic18fxx8 devices (byte address 3fffffh) rrrrrrrr dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 bit 7 bit 0 bit 7-5 dev2:dev0: device id bits these bits are used with the dev<10:3> bits in the device id register 2 to identify the part number. 000 = pic18f248 001 = pic18f448 010 = pic18f258 011 = pic18f458 bit 4-0 rev4:rev0: revision id bits these bits are used to indicate the device revision. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state rrrrrrrr dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 bit 7 bit 0 bit 7-0 dev10:dev3: device id bits these bits are used with the dev<2:0> bits in the device id register 1 to identify the part number. 00001000 = pic18fxx8 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state pic18fxx8 ds41159e-page 272 ? 2006 microchip technology inc. 24.2 watchdog timer (wdt) the watchdog timer is a free running, on-chip rc oscillator which does not require any external com- ponents. this rc oscillator is separate from the rc oscillator of the osc1/clki pin. that means that the wdt will run, even if the clock on the osc1/clki and osc2/clko/ra6 pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watchdog timer wake-up). the to bit in the rcon register will be cleared upon a wdt time-out. the watchdog timer is enabled/disabled by a device configuration bit. if the wdt is enabled, software execution may not disable this function. when the wdten configuration bit is cleared, the swdten bit enables/disables the operation of the wdt. the wdt time-out period values may be found in section 27.0 ?electrical characteristics? under parameter #31. values for the wdt postscaler may be assigned using the configuration bits. 24.2.1 control register register 24-13 shows the wdtcon register. this is a readable and writable register which contains a control bit that allows software to override the wdt enable configuration bit only when the configuration bit has disabled the wdt. register 24-13: wdtcon: watchdog timer control register note: the clrwdt and sleep instructions clear the wdt and the postscaler if assigned to the wdt and prevent it from timing out and generating a device reset condition. note: when a clrwdt instruction is executed and the postscaler is assigned to the wdt, the postscaler count will be cleared but the postscaler assignment is not changed. u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?swdten bit 7 bit 0 bit 7-1 unimplemented : read as ? 0 ? bit 0 swdten: software controlled watchdog timer enable bit 1 = watchdog timer is on 0 = watchdog timer is turned off if the wdten conf iguration bit in the configuration register = 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ? 2006 microchip technology inc. ds41159e-page 273 pic18fxx8 24.2.2 wdt postscaler the wdt has a postscaler that can extend the wdt reset period. the postscaler is selected at the time of device programming by the value written to the config2h configuration register. figure 24-1: watchdog timer block diagram table 24-2: summary of watchdog timer registers postscaler wdt timer wdten 8-to-1 mux wdtps2:wdtps0 wdt time-out 8 swdten bit configuration bit note: wdtps2:wdtps0 are bits in register config2h. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 config2h ? ? ? ? wdtps2 wdtps1 wdtps0 wdten rcon ipen ? ? ri to pd por bor wdtcon ? ? ? ? ? ? ?swdten legend: shaded cells are not used by the watchdog timer. pic18fxx8 ds41159e-page 274 ? 2006 microchip technology inc. 24.3 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit (rcon<2>) is cleared, the to bit (rcon<3>) is set and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, low or high-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd or v ss , ensure no external circuitry is drawing current from the i/o pin, power-down the a/d and disable external clocks. pull all i/o pins that are high-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should be considered. the mclr pin must be at a logic high level (v ihmc ). 24.3.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change or a peripheral interrupt. the following peripheral interrupts can wake the device from sleep: 1. psp read or write. 2. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 3. tmr3 interrupt. timer3 must be operating as an asynchronous counter. 4. ccp capture mode interrupt. 5. special event trigger (timer1 in asynchronous mode using an external clock). 6. mssp (start/stop) bit detect interrupt. 7. mssp transmit or receive in slave mode (spi/i 2 c). 8. usart rx or tx (synchronous slave mode). 9. a/d conversion (when a/d clock source is rc). 10. eeprom write operation complete. 11. lvd interrupt. other peripherals cannot generate interrupts, since during sleep, no on-chip clocks are present. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and will cause a ?wake-up?. the to and pd bits in the rcon register can be used to determine the cause of the device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred (and caused wake-up). when the sleep instruction is being executed, the next instruction (pc + 2) is prefetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address. in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 24.3.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if an interrupt condition (interrupt flag bit and interrupt enable bits are set) occurs before the execution of a sleep instruction, the sleep instruction will complete as a nop . therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and the pd bit will not be cleared. ? if the interrupt condition occurs during or after the execution of a sleep instruction, the device will immediately wake-up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruction should be executed before a sleep instruction. ? 2006 microchip technology inc. ds41159e-page 275 pic18fxx8 figure 24-2: wake-up from sleep through interrupt (1,2) q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clko (4) int pin intf flag (intcon<1>) gieh bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc + 2 pc + 4 inst(pc) = sleep inst(pc ? 1) inst(pc + 2) sleep processor in sleep interrupt latency (3) inst(pc + 4) inst(pc + 2) inst(0008h) inst(000ah) inst(0008h) dummy cycle pc + 4 0008h 000ah dummy cycle t ost (2) pc + 4 note 1: xt, hs or lp oscillator mode assumed. 2: gie = 1 assumed. in this case, after wake-up, the pr ocessor jumps to the interrupt routine. if gie = 0 , execution will continue in-line. 3: t ost = 1024 t osc (drawing not to scale). this delay will not occur for rc and ec oscillator modes. 4: clko is not available in these oscillator modes but shown here for timing reference. pic18fxx8 ds41159e-page 276 ? 2006 microchip technology inc. 24.4 program verification and code protection the overall structure of the code protection on the pic18 flash devices differs significantly from other picmicro devices. the user program memory is divided into five blocks. one of these is a boot block of 512 bytes. the remain- der of the memory is divided into four blocks on binary boundaries. each of the five blocks has three code protection bits associated with them. they are: ? code-protect bit (cpn) ? write-protect bit (wrtn) ? external block table read bit (ebtrn) figure 24-3 shows the program memory organization for 16 and 32-kbyte devices and the specific code protection bit associated with each block. the actual locations of the bits are summarized in table 24-3. figure 24-3: code-protected pr ogram memory for pic18fxx8 table 24-3: summary of code protection registers memory size/device block code protection controlled by: 16 kbytes (pic18fx48) 32 kbytes (pic18fx58) address range boot block boot block 000000h 0001ffh cpb, wrtb, ebtrb block 0 block 0 000200h 001fffh cp0, wrt0, ebtr0 block 1 block 1 002000h 003fffh cp1, wrt1, ebtr1 unimplemented read ? 0 ?s block 2 004000h 005fffh cp2, wrt2, ebtr2 unimplemented read ? 0 ?s block 3 006000h 007fffh cp3, wrt3, ebtr3 unimplemented read ? 0 ?s unimplemented read ? 0 ?s 008000h 1fffffh (unimplemented memory space) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 300008h config5l ? ? ? ? cp3 cp2 cp1 cp0 300009h config5h cpd cpb ? ? ? ? ? ? 30000ah config6l ? ? ? ? wrt3 wrt2 wrt1 wrt0 30000bh config6h wrtd wrtb wrtc ? ? ? ? ? 30000ch config7l ? ? ? ? ebtr3 ebtr2 ebtr1 ebtr0 30000dh config7h ?ebtrb ? ? ? ? ? ? legend: shaded cells are unimplemented. ? 2006 microchip technology inc. ds41159e-page 277 pic18fxx8 24.4.1 program memory code protection the user memory may be read to or written from any location using the table read and table write instruc- tions. the device id may be read with table reads. the configuration registers may be read and written with the table read and table write instructions. in user mode, the cpn bits have no direct effect. cpn bits inhibit external reads and writes. a block of user memory may be protected from table writes if the wrtn configuration bit is ? 0 ?. the ebtrn bits control table reads. for a block of user memory with the ebtrn bit set to ? 0 ?, a table read instruction that executes from within that block is allowed to read. a table read instruction that executes from a location outside of that block is not allowed to read and will result in reading ? 0 ?s. figures 24-4 through 24-6 illustrate table write and table read protection. figure 24-4: table write (wrtn) disallowed note: code protection bits may only be written to a ? 0 ? from a ? 1 ? state. it is not possible to write a ? 1 ? to a bit in the ? 0 ? state. code protection bits are only set to ? 1 ? by a full chip erase or block erase function. the full chip erase and block erase functions can only be initiated via icsp or an external programmer. 000000h 0001ffh 000200h 001fffh 002000h 003fffh 004000h 005fffh 006000h 007fffh wrtb, ebtrb = 11 wrt0, ebtr0 = 01 wrt1, ebtr1 = 11 wrt2, ebtr2 = 11 wrt3, ebtr3 = 11 tblwt * tblptr = 000fff pc = 001ffe tblwt * pc = 004ffe register values program memory configuration bit settings results: all table writes disabled to blockn whenever wrtn = 0 . pic18fxx8 ds41159e-page 278 ? 2006 microchip technology inc. figure 24-5: external block t able read (ebtrn) disallowed figure 24-6: external block table read (ebtrn) allowed 000000h 0001ffh 000200h 001fffh 002000h 003fffh 004000h 005fffh 006000h 007fffh wrtb, ebtrb = 11 wrt0, ebtr0 = 10 wrt1, ebtr1 = 11 wrt2, ebtr2 = 11 wrt3, ebtr3 = 11 tblrd * tblptr = 000fff pc = 002ffe results: all table reads from external blocks to blockn are disabled whenever ebtrn = 0 . tablat register returns a value of ? 0 ?. register values program memory configuration bit settings 000000h 0001ffh 000200h 001fffh 002000h 003fffh 004000h 005fffh 006000h 007fffh wrtb, ebtrb = 11 wrt0, ebtr0 = 10 wrt1, ebtr1 = 11 wrt2, ebtr2 = 11 wrt3, ebtr3 = 11 tblrd * tblptr = 000fff pc = 001ffe register values program memory configuration bit settings results: table reads permitted within blockn even when ebtrbn = 0 . tablat register returns the value of the data at the location tblptr. ? 2006 microchip technology inc. ds41159e-page 279 pic18fxx8 24.4.2 data eeprom code protection the entire data eeprom is protected from external reads and writes by two bits: cpd and wrtd. cpd inhibits external reads and writes of data eeprom. wrtd inhibits external writes to data eeprom. the cpu can continue to read and write data eeprom regardless of the protection bit settings. 24.4.3 configuration register protection the configuration registers can be write-protected. the wrtc bit controls protection of the configuration registers. in user mode, the wrtc bit is readable only. wrtc can only be written via icsp or an external programmer. 24.5 id locations eight memory locations (200000h-200007h) are designated as id locations where the user can store checksum or other code identification numbers. these locations are accessible during normal execution through the tblrd and tblwt instructions or during program/verify. the id locations can be read when the device is code-protected. 24.6 in-circuit serial programming pic18fxxx microcontrollers can be serially pro- grammed while in the end application circuit. this is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. 24.7 in-circuit debugger when the debug bit in configuration register, config4l, is programmed to a ? 0 ?, the in-circuit debugger functionality is enabled. this function allows simple debugging functions when used with mplab ? ide. when the microcontroller has this fea- ture enabled, some of the resources are not available for general use. resources used include 2 i/o pins, stack locations, program memory and data memory. for more information on the resources required, see the user?s guide for the in-circuit debugger you are using. to use the in-circuit debugger function of the micro- controller, the design must implement in-circuit serial programming connections to mclr /v pp , v dd , gnd, rb7 and rb6. this will interface to the in-circuit debugger module available from microchip or one of the third party development tool companies. the microchip in-circuit debugger (icd) used with the pic18fxxx microcontrollers is the mplab ? icd 2. 24.8 low-voltage icsp programming the lvp bit in configuration register, config4l, enables low-voltage icsp programming. this mode allows the microcontroller to be programmed via icsp using a v dd source in the operating voltage range. this only means that v pp does not have to be brought to v ihh but can instead be left at the normal operating voltage. in this mode, the rb5/pgm pin is dedicated to the programming function and ceases to be a general purpose i/o pin. during programming, v dd is applied to the mclr /v pp pin. to enter programming mode, v dd must be applied to the rb5/pgm pin, provided the lvp bit is set. the lvp bit defaults to a (? 1 ?) from the factory. if low-voltage programming mode is not used, the lvp bit can be programmed to a ? 0 ? and rb5/pgm becomes a digital i/o pin. however, the lvp bit may only be programmed when programming is entered with v ihh on mclr /v pp . the lvp bit can only be charged when using high voltage on mclr . it should be noted that once the lvp bit is programmed to ? 0 ?, only the high-voltage programming mode is available and only high-voltage programming mode can be used to program the device. when using low-voltage icsp programming, the part must be supplied 4.5v to 5.5v if a bulk erase will be executed. this includes reprogramming of the code- protect bits from an on state to an off state. for all other cases of low-voltage icsp programming, the part may be programmed at the normal operating voltage. this means unique user ids or user code can be reprogrammed or added. note 1: the high-voltage programming mode is always available, regardless of the state of the lvp bit, by applying v ihh to the mclr pin. 2: while in low-voltage icsp mode, the rb5 pin can no longer be used as a general purpose i/o pin. 3: when using low-voltage icsp program- ming (lvp) and the pull-ups on portb are enabled, bit 5 in the trisb register must be cleared to disable the pull-up on rb5 and ensure the proper operation of the device. pic18fxx8 ds41159e-page 280 ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. ds41159e-page 281 pic18fxx8 25.0 instruction set summary the pic18 instruction set adds many enhancements to the previous picmicro instruction sets, while maintaining an easy migration from these picmicro instruction sets. most instructions are a single program memory word (16 bits) but there are three instructions that require two program memory locations. each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into four basic categories: ? byte-oriented operations ? bit-oriented operations ? literal operations ? control operations the pic18 instruction set summary in table 25-2 lists byte-oriented , bit-oriented , literal and control operations. table 25-1 shows the opcode field descriptions. most byte-oriented instructions have three operands: 1. the file register (specified by ?f?) 2. the destination of the result (specified by ?d?) 3. the accessed memory (specified by ?a?) the file register designator ?f? specifies which file register is to be used by the instruction. the destination designator ?d? specifies where the result of the operation is to be placed. if ?d? is zero, the result is placed in the wreg register. if ?d? is one, the result is placed in the file register specified in the instruction. all bit-oriented instructions have three operands: 1. the file register (specified by ?f?) 2. the bit in the file register (specified by ?b?) 3. the accessed memory (specified by ?a?) the bit field designator ?b? selects the number of the bit affected by the operation, while the file register desig- nator ?f? represents the number of the file in which the bit is located. the literal instructions may use some of the following operands: ? a literal value to be loaded into a file register (specified by ?k?) ? the desired fsr register to load the literal value into (specified by ?f?) ? no operand required (specified by ???) the control instructions may use some of the following operands: ? a program memory address (specified by ?n?) ? the mode of the call or return instructions (specified by ?s?) ? the mode of the table read and table write instructions (specified by ?m?) ? no operand required (specified by ???) all instructions are a single word, except for three double-word instructions. these three instructions were made double-word instructions so that all the required information is available in these 32 bits. in the second word, the 4 msbs are ? 1 ?s. if this second word is executed as an instruction (by itself), it will execute as a nop . all single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a nop . the double-word instructions execute in two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. two-word branch instructions (if true) would take 3 s. figure 25-1 shows the general formats that the instructions can have. all examples use the format ? nnh ? to represent a hexa- decimal number, where ? h ? signifies a hexadecimal digit. the instruction set summary, shown in table 25-2, lists the instructions recognized by the microchip mpasm tm assembler. section 25.2 ?instruction set? provides a description of each instruction. 25.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (r-m-w) operation. the register is read, the data is modified and the result is stored according to either the instruction or the destination designator ?d?. a read operation is performed on a register even if the instruction writes to that register. for example, a ? clrf portb ? instruction will read portb, clear all the data bits, then write the result back to portb. this example would have the unintended result that the condition that sets the rbif flag would be cleared. pic18fxx8 ds41159e-page 282 ? 2006 microchip technology inc. table 25-1: opcode field descriptions field description a ram access bit: a = 0 : ram location in access ram (bsr register is ignored) a = 1 : ram bank is specified by bsr register bbb bit address within an 8-bit file register (0 to 7). bsr bank select register. used to select the current ram bank. d destination select bit: d = 0 : store result in wreg d = 1 : store result in file register f dest destination either the wreg register or the specified register file location. f 8-bit register file address (0x00 to 0xff). fs 12-bit register file address (0x000 to 0xfff). this is the source address. fd 12-bit register file address (0x000 to 0xfff). this is the destination address. k literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label label name. mm the mode of the tblptr register for the table read and table write instructions. only used with table read and table write instructions: * no change to register (such as tblptr with table reads and writes) *+ post-increment register (such as tblptr with table reads and writes) *- post-decrement register (such as tblptr with table reads and writes) +* pre-increment register (such as tb lptr with table reads and writes) n the relative address (2?s complement number) for relative branch instructions or the direct address for call/branch and return instructions. prodh product of multiply high byte. prodl product of multiply low byte. s fast call/return mode select bit: s = 0 : do not update into/from shadow registers s = 1 : certain registers loaded into/from shadow registers (fast mode) u unused or unchanged. wreg working register (accumulator). x don?t care (0 or 1). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. tblptr 21-bit table pointer (points to a program memory location). tablat 8-bit table latch. tos top-of-stack. pc program counter pcl program counter low byte. pch program counter high byte. pclath program counter high byte latch. pclatu program counter upper byte latch. gie global interrupt enable bit. wdt watchdog timer. to time-out bit. pd power-down bit. c, dc, z, ov, n alu status bits: carry, digit carry, zero, overflow, negative. [ ] optional. ( ) contents. assigned to. < > register bit field. in the set of. italics user defined term (font is courier). ? 2006 microchip technology inc. ds41159e-page 283 pic18fxx8 figure 25-1: general format for instructions byte-oriented file register operations 15 10 9 8 7 0 d = 0 for result destination to be wreg register opcode d a f (file #) d = 1 for result destination to be file register (f) a = 0 to force access bank bit-oriented file register operations 15 12 11 9 8 7 0 opcode b (bit #) a f (file #) b = 3-bit position of bit in file register (f) literal operations 15 8 7 0 opcode k (literal) k = 8-bit immediate value byte to byte move operations (2-word) 15 12 11 0 opcode f (source file #) call, goto and branch operations 15 8 7 0 opcode n<7:0> (literal) n = 20-bit immediate value a = 1 for bsr to select bank f = 8-bit file register address a = 0 to force access bank a = 1 for bsr to select bank f = 8-bit file register address 15 12 11 0 1111 n<19:8> (literal) 15 12 11 0 1111 f (destination file #) f = 12-bit file register address control operations example instruction addwf myreg, w, b movff myreg1, myreg2 bsf myreg, bit, b movlw 0x7f goto label 15 8 7 0 opcode n<7:0> (literal) 15 12 11 0 n<19:8> (literal) call myfunc 15 11 10 0 opcode n<10:0> (literal) s = fast bit bra myfunc 15 8 7 0 opcode n<7:0> (literal) bc myfunc s pic18fxx8 ds41159e-page 284 ? 2006 microchip technology inc. table 25-2: pic18fxxx instruction set mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb byte-oriented file register operations addwf addwfc andwf clrf comf cpfseq cpfsgt cpfslt decf decfsz dcfsnz incf incfsz infsnz iorwf movf movff movwf mulwf negf rlcf rlncf rrcf rrncf setf subfwb subwf subwfb swapf tstfsz xorwf f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f s , f d f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a add wreg and f add wreg and carry bit to f and wreg with f clear f complement f compare f with wreg, skip = compare f with wreg, skip > compare f with wreg, skip < decrement f decrement f, skip if 0 decrement f, skip if not 0 increment f increment f, skip if 0 increment f, skip if not 0 inclusive or wreg with f move f move f s (source) to 1st word f d (destination) 2nd word move wreg to f multiply wreg with f negate f rotate left f through carry rotate left f (no carry) rotate right f through carry rotate right f (no carry) set f subtract f from wreg with borrow subtract wreg from f subtract wreg from f with borrow swap nibbles in f test f, skip if 0 exclusive or wreg with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z, ov, n c, dc, z, ov, n z, n z z, n none none none c, dc, z, ov, n none none c, dc, z, ov, n none none z, n z, n none none none c, dc, z, ov, n c, z, n z, n c, z, n z, n none c, dc, z, ov, n c, dc, z, ov, n c, dc, z, ov, n none none z, n 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1, 2 1, 2 1, 2 1, 2 4 1, 2 bit-oriented file register operations bcf bsf btfsc btfss btg f, b, a f, b, a f, b, a f, b, a f, d, a bit clear f bit set f bit test f, skip if clear bit test f, skip if set bit toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff none none none none none 1, 2 1, 2 3, 4 3, 4 1, 2 note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated. ? 2006 microchip technology inc. ds41159e-page 285 pic18fxx8 control operations bc bn bnc bnn bnov bnz bov bra bz call clrwdt daw goto nop nop pop push rcall reset retfie retlw return sleep n n n n n n n n n n, s ? ? n ? ? ? ? n s k s ? branch if carry branch if negative branch if not carry branch if not negative branch if not overflow branch if not zero branch if overflow branch unconditionally branch if zero call subroutine1st word 2nd word clear watchdog timer decimal adjust wreg go to address 1st word 2nd word no operation no operation pop top of return stack (tos) push top of return stack (tos) relative call software device reset return from interrupt enable return with literal in wreg return from subroutine go into standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 none none none none none none none none none none to , pd c none none none none none none all gie/gieh, peie/giel none none to , pd 4 table 25-2: pic18fxxx instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated. pic18fxx8 ds41159e-page 286 ? 2006 microchip technology inc. literal operations addlw andlw iorlw lfsr movlb movlw mullw retlw sublw xorlw k k k f, k k k k k k k add literal and wreg and literal with wreg inclusive or literal with wreg move literal (12-bit) 2nd word to fsrx 1st word move literal to bsr<3:0> move literal to wreg multiply literal with wreg return with literal in wreg subtract wreg from literal exclusive or literal with wreg 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z, ov, n z, n z, n none none none none none c, dc, z, ov, n z, n data memory ? program memory operations tblrd* tblrd*+ tblrd*- tblrd+* tblwt* tblwt*+ tblwt*- tblwt+* table read table read with post-increment table read with post-decrement table read with pre-increment ta b l e wr i t e table write with post-increment table write with post-decrement table write with pre-increment 2 2 (5) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 none none none none none none none none table 25-2: pic18fxxx instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated. ? 2006 microchip technology inc. ds41159e-page 287 pic18fxx8 25.2 instruction set addlw add literal to w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k w status affected: n, ov, c, dc, z encoding: 0000 1111 kkkk kkkk description: the contents of w are added to the 8-bit literal ?k? and the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: addlw 0x15 before instruction w = 0x10 after instruction w = 0x25 addwf add w to f syntax: [ label ] addwf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (w) + (f) dest status affected: n, ov, c, dc, z encoding: 0010 01da ffff ffff description: add w to register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected. if ?a? is ? 1 ?, the bsr is used. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: addwf reg, w before instruction w = 0x17 reg = 0xc2 after instruction w=0xd9 reg = 0xc2 pic18fxx8 ds41159e-page 288 ? 2006 microchip technology inc. addwfc add w and carry bit to f syntax: [ label ] addwfc f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (w) + (f) + (c) dest status affected: n, ov, c, dc, z encoding: 0010 00da ffff ffff description: add w, the carry flag and data memory location ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in data memory location ?f?. if ?a? is ? 0 ?, the access bank will be selected. if ?a? is ? 1 ?, the bsr will not be overridden. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: addwfc reg, w before instruction carry bit = 1 reg = 0x02 w = 0x4d after instruction carry bit = 0 reg = 0x02 w = 0x50 andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. k w status affected: n, z encoding: 0000 1011 kkkk kkkk description: the contents of w are anded with the 8-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: andlw 0x5f before instruction w=0xa3 after instruction w = 0x03 ? 2006 microchip technology inc. ds41159e-page 289 pic18fxx8 andwf and w with f syntax: [ label ] andwf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (w) .and. (f) dest status affected: n, z encoding: 0001 01da ffff ffff description: the contents of w are anded with register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected. if ?a? is ? 1 ?, the bsr will not be overridden (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: andwf reg, w before instruction w = 0x17 reg = 0xc2 after instruction w = 0x02 reg = 0xc2 bc branch if carry syntax: [ label ] bc n operands: -128 n 127 operation: if carry bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0010 nnnn nnnn description: if the carry bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruc- tion, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bc jump before instruction pc = address (here) after instruction if carry = 1; pc = address (jump) if carry = 0; pc = address (here + 2) pic18fxx8 ds41159e-page 290 ? 2006 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f,b[,a] operands: 0 f 255 0 b 7 a [0,1] operation: 0 f status affected: none encoding: 1001 bbba ffff ffff description: bit ?b? in register ?f? is cleared. if ?a? is ? 0 ?, the access bank will be selected, over- riding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47 bn branch if negative syntax: [ label ] bn n operands: -128 n 127 operation: if negative bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0110 nnnn nnnn description: if the negative bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruc- tion, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bn jump before instruction pc = address (here) after instruction if negative = 1; pc = address (jump) if negative = 0; pc = address (here + 2) ? 2006 microchip technology inc. ds41159e-page 291 pic18fxx8 bnc branch if not carry syntax: [ label ] bnc n operands: -128 n 127 operation: if carry bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0011 nnnn nnnn description: if the carry bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruc- tion, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnc jump before instruction pc = address (here) after instruction if carry = 0; pc = address (jump) if carry = 1; pc = address (here + 2) bnn branch if not negative syntax: [ label ] bnn n operands: -128 n 127 operation: if negative bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0111 nnnn nnnn description: if the negative bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruc- tion, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnn jump before instruction pc = address (here) after instruction if negative = 0; pc = address (jump) if negative = 1; pc = address (here + 2) pic18fxx8 ds41159e-page 292 ? 2006 microchip technology inc. bnov branch if not overflow syntax: [ label ] bnov n operands: -128 n 127 operation: if overflow bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0101 nnnn nnnn description: if the overflow bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruc- tion, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnov jump before instruction pc = address (here) after instruction if overflow = 0; pc = address (jump) if overflow = 1; pc = address (here + 2) bnz branch if not zero syntax: [ label ] bnz n operands: -128 n 127 operation: if zero bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0001 nnnn nnnn description: if the zero bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruc- tion, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnz jump before instruction pc = address (here) after instruction if zero = 0; pc = address (jump) if zero = 1; pc = address (here + 2) ? 2006 microchip technology inc. ds41159e-page 293 pic18fxx8 bra unconditional branch syntax: [ label ] bra n operands: -1024 n 1023 operation: (pc) + 2 + 2n pc status affected: none encoding: 1101 0nnn nnnn nnnn description: add the 2?s complement number ?2n? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation example: here bra jump before instruction pc = address (here) after instruction pc = address (jump) bsf bit set f syntax: [ label ] bsf f,b[,a] operands: 0 f 255 0 b 7 a [0,1] operation: 1 f status affected: none encoding: 1000 bbba ffff ffff description: bit ?b? in register ?f? is set. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a pic18fxx8 ds41159e-page 294 ? 2006 microchip technology inc. btfsc bit test file, skip if clear syntax: [ label ] btfsc f,b[,a] operands: 0 f 255 0 b 7 a [0,1] operation: skip if (f) = 0 status affected: none encoding: 1011 bbba ffff ffff description: if bit ?b? in register ?f? is ? 0 ?, then the next instruction is skipped. if bit ?b? is ? 0 ?, then the next instruction fetched during the current instruction execution is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here false true btfsc : : flag, 1 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (true) if flag<1> = 1; pc = address (false) btfss bit test file, skip if set syntax: [ label ] btfss f,b[,a] operands: 0 f 255 0 b 7 a [0,1] operation: skip if (f) = 1 status affected: none encoding: 1010 bbba ffff ffff description: if bit ?b? in register ?f? is ? 1 ?, then the next instruction is skipped. if bit ?b? is ? 1 ?, then the next instruction fetched during the current instruction execution is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here false true btfss : : flag, 1 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (false) if flag<1> = 1; pc = address (true) ? 2006 microchip technology inc. ds41159e-page 295 pic18fxx8 btg bit toggle f syntax: [ label ] btg f,b[,a] operands: 0 f 255 0 b 7 a [0,1] operation: (f ) f status affected: none encoding: 0111 bbba ffff ffff description: bit ?b? in data memory location ?f? is inverted. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: btg portc, 4 before instruction: portc = 0111 0101 [0x75] after instruction: portc = 0110 0101 [0x65] bov branch if overflow syntax: [ label ] bov n operands: -128 n 127 operation: if overflow bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0100 nnnn nnnn description: if the overflow bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruc- tion, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bov jump before instruction pc = address (here) after instruction if overflow = 1; pc = address (jump) if overflow = 0; pc = address (here + 2) pic18fxx8 ds41159e-page 296 ? 2006 microchip technology inc. bz branch if zero syntax: [ label ] bz n operands: -128 n 127 operation: if zero bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0000 nnnn nnnn description: if the zero bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruc- tion, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bz jump before instruction pc = address (here) after instruction if zero = 1; pc = address (jump) if zero = 0; pc = address (here + 2) call subroutine call syntax: [ label ] call k [,s] operands: 0 k 1048575 s [0,1] operation: (pc) + 4 tos, k pc<20:1>, if s = 1 (w) ws, (status) statuss, (bsr) bsrs status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 110s k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: subroutine call of entire 2-mbyte memory range. first, return address (pc + 4) is pushed onto the return stack. if ?s? = 1 , the w, status and bsr registers are also pushed into their respective shadow registers, ws, statuss and bsrs. if ?s? = 0 , no update occurs (default). then, the 20-bit value ?k? is loaded into pc<20:1>. call is a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k?<7:0>, push pc to stack read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example: here call there,fast before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 4) ws = w bsrs = bsr statuss= status ? 2006 microchip technology inc. ds41159e-page 297 pic18fxx8 clrf clear f syntax: [ label ] clrf f [,a] operands: 0 f 255 a [0,1] operation: 000h f 1 z status affected: z encoding: 0110 101a ffff ffff description: clears the contents of the specified register. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 000h wdt, 000h wdt postscaler, 1 to, 1 pd status affected: to , pd encoding: 0000 0000 0000 0100 description: clrwdt instruction resets the watchdog timer. it also resets the postscaler of the wdt. status bits to and pd are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data no operation example: clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt postscaler = 0 to =1 pd =1 pic18fxx8 ds41159e-page 298 ? 2006 microchip technology inc. comf complement f syntax: [ label ] comf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: dest status affected: n, z encoding: 0001 11da ffff ffff description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: comf reg, w before instruction reg = 0x13 after instruction reg = 0x13 w=0xec (f) cpfseq compare f with w, skip if f = w syntax: [ label ] cpfseq f [,a] operands: 0 f 255 a [0,1] operation: (f) ? (w), skip if (f) = (w) (unsigned comparison) status affected: none encoding: 0110 001a ffff ffff description: compares the contents of data memory location ?f? to the contents of w by performing an unsigned subtraction. if ?f? = w , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfseq reg nequal : equal : before instruction pc address = here w=? reg = ? after instruction if reg = w; pc = address (equal) if reg w; pc = address (nequal) ? 2006 microchip technology inc. ds41159e-page 299 pic18fxx8 cpfsgt compare f with w, skip if f > w syntax: [ label ] cpfsgt f [,a] operands: 0 f 255 a [0,1] operation: (f) ? ( w), skip if (f) > (w) (unsigned comparison) status affected: none encoding: 0110 010a ffff ffff description: compares the contents of data memory location ?f? to the contents of the w by performing an unsigned subtraction. if the contents of ?f? are greater than the contents of wreg , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfsgt reg ngreater : greater : before instruction pc = address (here) w= ? after instruction if reg > w; pc = address (greater) if reg w; pc = address (ngreater) cpfslt compare f with w, skip if f < w syntax: [ label ] cpfslt f [,a] operands: 0 f 255 a [0,1] operation: (f) ? ( w), skip if (f) < (w) (unsigned comparison) status affected: none encoding: 0110 000a ffff ffff description: compares the contents of data memory location ?f? to the contents of w by performing an unsigned subtraction. if the contents of ?f? are less than the contents of w, then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected. if ?a? is ? 1 ?, the bsr will not be overridden (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfslt reg nless : less : before instruction pc = address (here) w= ? after instruction if reg < w; pc = address (less) if reg w; pc = address (nless) pic18fxx8 ds41159e-page 300 ? 2006 microchip technology inc. daw decimal adjust w register syntax: [ label ] daw operands: none operation: if [w<3:0> > 9] or [dc = 1 ] then (w<3:0>) + 6 w<3:0>; else ( w<3:0>) w<3:0> if [w<7:4> > 9] or [c = 1 ] then ( w<7:4>) + 6 w<7:4>; else (w<7:4>) w<7:4> status affected: c encoding: 0000 0000 0000 0111 description: daw adjusts the eight-bit value in w resulting from the earlier addition of two variables (each in packed bcd format) and produces a correct packed bcd result. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register w process data write w exam ple 1: daw before instruction w=0xa5 c=0 dc = 0 after instruction w = 0x05 c=1 dc = 0 example 2: before instruction w=0xce c=0 dc = 0 after instruction w = 0x34 c=1 dc = 0 decf decrement f syntax: [ label ] decf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest status affected: c, dc, n, ov, z encoding: 0000 01da ffff ffff description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: decf cnt, before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1 ? 2006 microchip technology inc. ds41159e-page 301 pic18fxx8 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest, skip if result = 0 status affected: none encoding: 0010 11da ffff ffff description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here decfsz cnt goto loop continue before instruction pc = address (here) after instruction cnt = cnt ? 1 if cnt = 0; pc = address (continue) if cnt 0; pc = address (here + 2) dcfsnz decrement f, skip if not 0 syntax: [ label ] dcfsnz f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest, skip if result 0 status affected: none encoding: 0100 11da ffff ffff description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is not ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here dcfsnz temp zero : nzero : before instruction temp = ? after instruction temp = temp ? 1, if temp = 0; pc = address (zero) if temp 0; pc = address (nzero) pic18fxx8 ds41159e-page 302 ? 2006 microchip technology inc. goto unconditional branch syntax: [ label ] goto k operands: 0 k 1048575 operation: k pc<20:1> status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: goto allows an unconditional branch anywhere within entire 2-mbyte memory range. the 20-bit value ?k? is loaded into pc<20:1>. goto is always a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k?<7:0> no operation read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example: goto there after instruction pc = address (there) incf increment f syntax: [ label ] incf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest status affected: c, dc, n, ov, z encoding: 0010 10da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: incf cnt, before instruction cnt = 0xff z=0 c=? dc = ? after instruction cnt = 0x00 z=1 c=1 dc = 1 ? 2006 microchip technology inc. ds41159e-page 303 pic18fxx8 incfsz increment f, skip if 0 syntax: [ label ] incfsz f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest, skip if result = 0 status affected: none encoding: 0011 11da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here incfsz cnt nzero : zero : before instruction pc = address (here) after instruction cnt = cnt + 1 if cnt = 0; pc = address (zero) if cnt 0; pc = address (nzero) infsnz increment f, skip if not 0 syntax: [ label ] infsnz f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest, skip if result 0 status affected: none encoding: 0100 10da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is not ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here infsnz reg zero nzero before instruction pc = address (here) after instruction reg = reg + 1 if reg 0; pc = address (nzero) if reg = 0; pc = address (zero) pic18fxx8 ds41159e-page 304 ? 2006 microchip technology inc. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k w status affected: n, z encoding: 0000 1001 kkkk kkkk description: the contents of w are ored with the eight-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: iorlw 0x35 before instruction w = 0x9a after instruction w=0xbf iorwf inclusive or w with f syntax: [ label ] iorwf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (w) .or. (f) dest status affected: n, z encoding: 0001 00da ffff ffff description: inclusive or w with register ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: iorwf result, w before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93 ? 2006 microchip technology inc. ds41159e-page 305 pic18fxx8 lfsr load fsr syntax: [ label ] lfsr f,k operands: 0 f 2 0 k 4095 operation: k fsrf status affected: none encoding: 1110 1111 1110 0000 00ff k 7 kkk k 11 kkk kkkk description: the 12-bit literal ?k? is loaded into the file select register pointed to by ?f?. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? msb process data write literal ?k? msb to fsrfh decode read literal ?k? lsb process data write literal ?k? to fsrfl example: lfsr 2, 0x3ab after instruction fsr2h = 0x03 fsr2l = 0xab movf move f syntax: [ label ] movf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: f dest status affected: n, z encoding: 0101 00da ffff ffff description: the contents of register ?f? are moved to a destination dependent upon the status of ?d?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). location ?f? can be anywhere in the 256-byte bank. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write w example: movf reg, w before instruction reg = 0x22 w=0xff after instruction reg = 0x22 w = 0x22 pic18fxx8 ds41159e-page 306 ? 2006 microchip technology inc. movff move f to f syntax: [ label ] movff f s ,f d operands: 0 f s 4095 0 f d 4095 operation: (f s ) f d status affected: none encoding: 1st word (source) 2nd word (destin.) 1100 1111 ffff ffff ffff ffff ffff s ffff d description: the contents of source register ?f s ? are moved to destination register ?f d ?. location of source ?f s ? can be anywhere in the 4096-byte data space (000h to fffh) and location of destination ?f d ? can also be anywhere from 000h to fffh. either source or destination can be w (a useful special situation). movff is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an i/o port). the movff instruction cannot use the pcl, tosu, tosh or tosl as the destination register. the movff instruction should not be used to modify interrupt settings while any interrupt is enabled (see page 77). words: 2 cycles: 2 (3) q cycle activity: q1 q2 q3 q4 decode read register ?f? (src) process data no operation decode no operation no dummy read no operation write register ?f? (dest) example: movff reg1, reg2 before instruction reg1 = 0x33 reg2 = 0x11 after instruction reg1 = 0x33 reg2 = 0x33 movlb move literal to low nibble in bsr syntax: [ label ] movlb k operands: 0 k 255 operation: k bsr status affected: none encoding: 0000 0001 kkkk kkkk description: the 8-bit literal ?k? is loaded into the bank select register (bsr). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write literal ?k? to bsr example: movlb 5 before instruction bsr register = 0x02 after instruction bsr register = 0x05 ? 2006 microchip technology inc. ds41159e-page 307 pic18fxx8 movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k w status affected: none encoding: 0000 1110 kkkk kkkk description: the eight-bit literal ?k? is loaded into w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f [,a] operands: 0 f 255 a [0,1] operation: (w) f status affected: none encoding: 0110 111a ffff ffff description: move data from w to register ?f?. location ?f? can be anywhere in the 256-byte bank. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: movwf reg before instruction w = 0x4f reg = 0xff after instruction w = 0x4f reg = 0x4f pic18fxx8 ds41159e-page 308 ? 2006 microchip technology inc. mullw multiply literal with w syntax: [ label ] mullw k operands: 0 k 255 operation: (w) x k prodh:prodl status affected: none encoding: 0000 1101 kkkk kkkk description: an unsigned multiplication is carried out between the contents of w and the 8-bit literal ?k?. the 16-bit result is placed in the prodh:prodl register pair. prodh contains the high byte. w is unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write registers prodh: prodl example: mullw 0xc4 before instruction w=0xe2 prodh = ? prodl = ? after instruction w=0xe2 prodh = 0xad prodl = 0x08 mulwf multiply w with f syntax: [ label ] mulwf f [,a] operands: 0 f 255 a [0,1] operation: (w) x (f) prodh:prodl status affected: none encoding: 0000 001a ffff ffff description: an unsigned multiplication is carried out between the contents of w and the register file location ?f?. the 16-bit result is stored in the prodh:prodl register pair. prodh contains the high byte. both w and ?f? are unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a?= 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write registers prodh: prodl example: mulwf reg before instruction w=0xc4 reg = 0xb5 prodh = ? prodl = ? after instruction w=0xc4 reg = 0xb5 prodh = 0x8a prodl = 0x94 ? 2006 microchip technology inc. ds41159e-page 309 pic18fxx8 negf negate f syntax: [ label ] negf f [,a] operands: 0 f 255 a [0,1] operation: ( f ) + 1 f status affected: n, ov, c, dc, z encoding: 0110 110a ffff ffff description: location ?f? is negated using two?s complement. the result is placed in the data memory location ?f?. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: negf reg, 1 before instruction reg = 0011 1010 [0x3a] after instruction reg = 1100 0110 [0xc6] nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation example: none. pic18fxx8 ds41159e-page 310 ? 2006 microchip technology inc. pop pop top of return stack syntax: [ label ] pop operands: none operation: (tos) bit bucket status affected: none encoding: 0000 0000 0000 0110 description: the tos value is pulled off the return stack and is discarded. the tos value then becomes the previous value that was pushed onto the return stack. this instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation pop tos value no operation example: pop goto new before instruction tos = 0x0031a2 stack (1 level down) = 0x014332 after instruction tos = 0x014332 pc = new push push top of return stack syntax: [ label ] push operands: none operation: (pc + 2) tos status affected: none encoding: 0000 0000 0000 0101 description: the pc + 2 is pushed onto the top of the return stack. the previous tos value is pushed down on the stack. this instruction allows the user to implement a software stack by modifying tos and then pushing it onto the return stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode push pc + 2 onto return stack no operation no operation example: push before instruction tos = 0x00345a pc = 0x000124 after instruction pc = 0x000126 tos = 0x000126 stack (1 level down) = 0x00345a ? 2006 microchip technology inc. ds41159e-page 311 pic18fxx8 rcall relative call syntax: [ label ] rcall n operands: -1024 n 1023 operation: (pc) + 2 tos, (pc) + 2 + 2n pc status affected: none encoding: 1101 1nnn nnnn nnnn description: subroutine call with a jump up to 1k from the current location. first, return address (pc + 2) is pushed onto the stack. then, add the 2?s complement number ?2n? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?n? push pc to stack process data write to pc no operation no operation no operation no operation example : here rcall jump before instruction pc = address (here) after instruction pc = address (jump) tos = address (here + 2) reset reset syntax: [ label ] reset operands: none operation: reset all registers and flags that are affected by a mclr reset. status affected: all encoding: 0000 0000 1111 1111 description: this instruction provides a way to execute a mclr reset in software. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode start reset no operation no operation example : reset after instruction registers = reset value flags* = reset value pic18fxx8 ds41159e-page 312 ? 2006 microchip technology inc. retfie return from interrupt syntax: [ label ] retfie [s] operands: s [0,1] operation: (tos) pc, 1 gie/gieh or peie/giel, if s = 1 (ws) w, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged. status affected: gie/gieh, peie/giel. encoding: 0000 0000 0001 000s description: return from interrupt. stack is popped and top-of-stack (tos) is loaded into the pc. interrupts are enabled by setting either the high or low priority global interrupt enable bit. if ?s? = 1 , the contents of the shadow registers ws, statuss and bsrs are loaded into their corresponding registers w, status and bsr. if ?s? = 0 , no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation pop pc from stack set gieh or giel no operation no operation no operation no operation example: retfie 1 after interrupt pc = tos w=ws bsr = bsrs status = statuss gie/gieh, peie/giel = 1 retlw return literal to w syntax: [ label ] retlw k operands: 0 k 255 operation: k w, (tos) pc, pclatu, pclath are unchanged status affected: none encoding: 0000 1100 kkkk kkkk description: w is loaded with the eight-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). the high address latch (pclath) remains unchanged. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data pop pc from stack, write to w no operation no operation no operation no operation example: call table ; w contains table ; offset value ; w now has ; table value : table addwf pcl ; w = offset retlw k0 ; begin table retlw k1 ; : : retlw kn ; end of table before instruction w = 0x07 after instruction w = value of kn ? 2006 microchip technology inc. ds41159e-page 313 pic18fxx8 return return from subroutine syntax: [ label ] return [s] operands: s [0,1] operation: (tos) pc, if s = 1 (ws) w, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged status affected: none encoding: 0000 0000 0001 001s description: return from subroutine. the stack is popped and the top of the stack (tos) is loaded into the program counter. if ?s?= 1 , the contents of the shadow registers ws, statuss and bsrs are loaded into their corresponding registers w, status and bsr. if ?s? = 0 , no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation process data pop pc from stack no operation no operation no operation no operation example: return after interrupt pc = tos rlcf rotate left f through carry syntax: [ label ] rlcf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f pic18fxx8 ds41159e-page 314 ? 2006 microchip technology inc. rlncf rotate left f (no carry) syntax: [ label ] rlncf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f ? 2006 microchip technology inc. ds41159e-page 315 pic18fxx8 rrncf rotate right f (no carry) syntax: [ label ] rrncf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f pic18fxx8 ds41159e-page 316 ? 2006 microchip technology inc. sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h wdt, 0 wdt postscaler, 1 to , 0 pd status affected: to , pd encoding: 0000 0000 0000 0011 description: the power-down status bit (pd ) is cleared. the time-out status bit (to ) is set. watchdog timer and its postscaler are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data go to sleep example: sleep before instruction to =? pd =? after instruction to =1 ? pd =0 ? if wdt causes wake-up, this bit is cleared. subfwb subtract f from w with borrow syntax: [ label ] subfwb f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (w) ? (f) ? (c ) dest status affected: n, ov, c, dc, z encoding: 0101 01da ffff ffff description: subtract register ?f? and carry flag (borrow) from w (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: subfwb reg before instruction reg = 0x03 w = 0x02 c = 0x01 after instruction reg = 0xff w = 0x02 c = 0x00 z = 0x00 n = 0x01 ; result is negative example 2: subfwb reg, 0, 0 before instruction reg = 2 w=5 c=1 after instruction reg = 2 w=3 c=1 z=0 n = 0 ; result is positive example 3: subfwb reg, 1, 0 before instruction reg = 1 w=2 c=0 after instruction reg = 0 w=2 c=1 z = 1 ; result is zero n=0 ? 2006 microchip technology inc. ds41159e-page 317 pic18fxx8 sublw subtract w from literal syntax: [ label ]sublw k operands: 0 k 255 operation: k ? (w) w status affected: n, ov, c, dc, z encoding: 0000 1000 kkkk kkkk description: w is subtracted from the eight-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example 1: sublw 0x02 before instruction w=1 c=? after instruction w=1 c = 1 ; result is positive z=0 n=0 example 2: sublw 0x02 before instruction w=2 c=? after instruction w=0 c = 1 ; result is zero z=1 n=0 example 3: sublw 0x02 before instruction w=3 c=? after instruction w = ff ; (2?s complement) c = 0 ; result is negative z=0 n=1 subwf subtract w from f syntax: [ label ] subwf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (w) dest status affected: n, ov, c, dc, z encoding: 0101 11da ffff ffff description: subtract w from register ?f? (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: subwf reg before instruction reg = 3 w=2 c=? after instruction reg = 1 w=2 c = 1 ; result is positive z=0 n=0 example 2: subwf reg, w before instruction reg = 2 w=2 c=? after instruction reg = 2 w=0 c = 1 ; result is zero z=1 n=0 example 3: subwf reg before instruction reg = 0x01 w = 0x02 c=? after instruction reg = 0xffh ;(2?s complement) w = 0x02 c = 0x00 ; result is negative z = 0x00 n = 0x01 pic18fxx8 ds41159e-page 318 ? 2006 microchip technology inc. subwfb subtract w from f with borrow syntax: [ label ] subwfb f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (w) ? (c ) dest status affected: n, ov, c, dc, z encoding: 0101 10da ffff ffff description: subtract w and the carry flag (borrow) from register ?f? (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: subwfb reg, 1, 0 before instruction reg = 0x19 (0001 1001) w = 0x0d (0000 1101) c = 0x01 after instruction reg = 0x0c (0000 1011) w = 0x0d (0000 1101) c = 0x01 z = 0x00 n = 0x00 ; result is positive example 2: subwfb reg, 0, 0 before instruction reg = 0x1b (0001 1011) w = 0x1a (0001 1010) c = 0x00 after instruction reg = 0x1b (0001 1011) w = 0x00 c = 0x01 z = 0x01 ; result is zero n = 0x00 example 3: subwfb reg, 1, 0 before instruction reg = 0x03 (0000 0011) w = 0x0e (0000 1101) c = 0x01 after instruction reg = 0xf5 (1111 0100) ; [2?s comp] w = 0x0e (0000 1101) c = 0x00 z = 0x00 n = 0x01 ; result is negative swapf swap f syntax: [ label ] swapf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> status affected: none encoding: 0011 10da ffff ffff description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: swapf reg before instruction reg = 0x53 after instruction reg = 0x35 ? 2006 microchip technology inc. ds41159e-page 319 pic18fxx8 tblrd table read syntax: [ label ] tblrd ( *; *+; *-; +*) operands: none operation: if tblrd *, (prog mem (tblptr)) tablat; tblptr ? no change; if tblrd *+, (prog mem (tblptr)) tablat; (tblptr) + 1 tblptr; if tblrd *-, (prog mem (tblptr)) tablat; (tblptr) ? 1 tblptr; if tblrd +*, (tblptr) + 1 tblptr; (prog mem (tblptr)) tablat status affected: none encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction is used to read the contents of program memory (p.m.). to address the program memory, a pointer called table pointer (tblptr) is used. the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. tblptr[0] = 0 : least significant byte of program memory word tblptr[0] = 1 : most significant byte of program memory word the tblrd instruction can modify the value of tblptr as follows: ? no change ? post-increment ? post-decrement ? pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read program memory) no operation no operation (write tablat) exampl e 1: tblrd *+ ; before instruction tablat = 0x55 tblptr = 0x00a356 memory(0x00a356) = 0x34 after instruction tablat = 0x34 tblptr = 0x00a357 exa mple 2: tblrd +* ; before instruction tablat = 0xaa tblptr = 0x01a357 memory(0x01a357) = 0x12 memory(0x01a358) = 0x34 after instruction tablat = 0x34 tblptr = 0x01a358 pic18fxx8 ds41159e-page 320 ? 2006 microchip technology inc. tblwt table write syntax: [ label ] tblwt ( *; *+; *-; +*) operands: none operation: if tblwt*, (tablat) holding register; tblptr ? no change; if tblwt*+, (tablat) holding register; (tblptr) + 1 tblptr; if tblwt*-, (tablat) holding register; (tblptr) ? 1 tblptr; if tblwt+*, (tblptr) + 1 tblptr; (tablat) holding register; status affected: none encoding: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction uses the 3 lsbs of tblptr to determine which of the 8 holding registers the tablat is written to. the holding registers are used to program the contents of program memory (p.m.). (refer to section 6.0 ?flash program memory? for additional details.) the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. the lsb of the tblptr selects which byte of the program memory location to access. tblptr[0] = 0 : least significant byte of program memory word tblptr[0] = 1 : most significant byte of program memory word the tblwt instruction can modify the value of tblptr as follows: ? no change ? post-increment ? post-decrement ? pre-increment tblwt table write (continued) words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read tablat) no operation no operation (write to holding register) exa m ple 1: tblwt *+; before instruction tablat = 0x55 tblptr = 0x00a356 holding register (0x00a356) = 0xff after instructions (table write completion) tablat = 0x55 tblptr = 0x00a357 holding register (0x00a356) = 0x55 examp le 2: tblwt +*; before instruction tablat = 0x34 tblptr = 0x01389a holding register (0x01389a) = 0xff holding register (0x01389b) = 0xff after instruction (table write completion) tablat = 0x34 tblptr = 0x01389b holding register (0x01389a) = 0xff holding register (0x01389b) = 0x34 ? 2006 microchip technology inc. ds41159e-page 321 pic18fxx8 tstfsz test f, skip if 0 syntax: [ label ] tstfsz f [,a] operands: 0 f 255 a [0,1] operation: skip if f = 0 status affected: none encoding: 0110 011a ffff ffff description: if ?f? = 0 , the next instruction fetched during the current instruction execution is discarded and a nop is executed, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here tstfsz cnt nzero : zero : before instruction pc = address (here) after instruction if cnt = 0x00, pc = address (zero) if cnt 0x00, pc = address (nzero) xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 k 255 operation: (w) .xor. k w status affected: n, z encoding: 0000 1010 kkkk kkkk description: the contents of w are xored with the 8-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: xorlw 0xaf before instruction w=0xb5 after instruction w = 0x1a pic18fxx8 ds41159e-page 322 ? 2006 microchip technology inc. xorwf exclusive or w with f syntax: [ label ] xorwf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (w) .xor. (f) dest status affected: n, z encoding: 0001 10da ffff ffff description: exclusive or the contents of w with register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: xorwf reg before instruction reg = 0xaf w=0xb5 after instruction reg = 0x1a w=0xb5 ? 2006 microchip technology inc. ds41159e-page 323 pic18fxx8 26.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian - mplab c30 c compiler - mplab asm30 assembler/linker/library ? simulators - mplab sim software simulator - mplab dspic30 software simulator ?emulators - mplab ice 2000 in-circuit emulator - mplab ice 4000 in-circuit emulator ? in-circuit debugger - mplab icd 2 ? device programmers -pro mate ? ii universal device programmer - picstart ? plus development programmer - mplab pm3 device programmer ? low-cost demonstration boards - picdem tm 1 demonstration board - picdem.net tm demonstration board - picdem 2 plus demonstration board - picdem 3 demonstration board - picdem 4 demonstration board - picdem 17 demonstration board - picdem 18r demonstration board - picdem lin demonstration board - picdem usb demonstration board ? evaluation kits -k ee l oq ? evaluation and programming tools - picdem msc -microid ? developer kits -can - powersmart ? developer kits -analog 26.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? based application that contains: ? an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? extensive on-line help the mplab ide allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to picmicro emulator and simulator tools (automatically updates all project information) ? debug using: - source files (assembly or c) - mixed assembly and c - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increasing flexibility and power. 26.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all picmicro mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol ref- erence, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process pic18fxx8 ds41159e-page 324 ? 2006 microchip technology inc. 26.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi c compilers for microchip?s pic17cxxx and pic18cxxx family of microcontrollers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 26.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 26.5 mplab c30 c compiler the mplab c30 c compiler is a full-featured, ansi compliant, optimizing compiler that translates standard ansi c programs into dspic30f assembly language source. the compiler also supports many command line options and language extensions to take full advantage of the dspic30f device hardware capabili- ties and afford fine control of the compiler code generator. mplab c30 is distributed with a complete ansi c standard library. all library functions have been vali- dated and conform to the ansi c library standard. the library includes functions for string manipulation, dynamic memory allocation, data conversion, time- keeping and math functions (trigonometric, exponential and hyperbolic). the compiler provides symbolic information for high-level source debugging with the mplab ide. 26.6 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 compiler uses the assembler to produce it?s object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire dspic30f instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility 26.7 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc hosted environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. the execu- tion can be performed in single-step, execute until break or trace mode. the mplab sim simulator fully supports symbolic debugging using the mplab c17 and mplab c18 c compilers, as well as the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. 26.8 mplab sim30 software simulator the mplab sim30 software simulator allows code development in a pc hosted environment by simulating the dspic30f series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. the mplab sim30 simulator fully supports symbolic debugging using the mplab c30 c compiler and mplab asm30 assembler. the simulator runs in either a command line mode for automated tasks, or from mplab ide. this high-speed simulator is designed to debug, analyze and optimize time intensive dsp routines. ? 2006 microchip technology inc. ds41159e-page 325 pic18fxx8 26.9 mplab ice 2000 high-performance universal in-circuit emulator the mplab ice 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 26.10 mplab ice 4000 high-performance universal in-circuit emulator the mplab ice 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high- end picmicro microcontrollers. software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab icd 4000 is a premium emulator system, providing the features of mplab ice 2000, but with increased emulation memory and high-speed perfor- mance for dspic30f and pic18xxxx devices. its advanced emulator features include complex triggering and timing, up to 2 mb of emulation memory and the ability to view variables in real-time. the mplab ice 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 26.11 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash picmicro mcus and can be used to develop for these and other picmicro microcontrollers. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost effective in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, cpu status and peripheral registers. running at full speed enables testing hardware and applications in real-time. mplab icd 2 also serves as a development programmer for selected picmicro devices. 26.12 pro mate ii universal device programmer the pro mate ii is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features an lcd display for instructions and error messages and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify and program picmicro devices without a pc connection. it can also set code protection in this mode. 26.13 mplab pm3 device programmer the mplab pm3 is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modular detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand- alone mode, the mplab pm3 device programmer can read, verify and program picmicro devices without a pc connection. it can also set code protection in this mode. mplab pm3 connects to the host pc via an rs- 232 or usb cable. mplab pm3 has high-speed com- munications and optimized algorithms for quick pro- gramming of large memory devices and incorporates an sd/mmc card for file storage and secure data appli- cations. pic18fxx8 ds41159e-page 326 ? 2006 microchip technology inc. 26.14 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most picmicro devices up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 26.15 picdem 1 picmicro demonstration board the picdem 1 demonstration board demonstrates the capabilities of the pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the sample microcontrollers provided with the picdem 1 demonstration board can be programmed with a pro mate ii device program- mer or a picstart plus development programmer. the picdem 1 demonstration board can be connected to the mplab ice in-circuit emulator for testing. a prototype area extends the circuitry for additional appli- cation components. features include an rs-232 interface, a potentiometer for simulated analog input, push button switches and eight leds. 26.16 picdem.net internet/ethernet demonstration board the picdem.net demonstration board is an internet/ ethernet demonstration board using the pic18f452 microcontroller and tcp/ip firmware. the board supports any 40-pin dip device that conforms to the standard pinout used by the pic16f877 or pic18c452. this kit features a user friendly tcp/ip stack, web server with html, a 24l256 serial eeprom for xmodem download to web pages into serial eeprom, icsp/mplab icd 2 interface con- nector, an ethernet interface, rs-232 interface and a 16 x 2 lcd display. also included is the book and cd-rom ?tcp/ip lean, web servers for embedded systems,? by jeremy bentham 26.17 picdem 2 plus demonstration board the picdem 2 plus demonstration board supports many 18, 28 and 40-pin microcontrollers, including pic16f87x and pic18fxx2 devices. all the neces- sary hardware and software is included to run the dem- onstration programs. the sample microcontrollers provided with the picdem 2 demonstration board can be programmed with a pro mate ii device program- mer, picstart plus development programmer, or mplab icd 2 with a universal programmer adapter. the mplab icd 2 and mplab ice in-circuit emulators may also be used with the picdem 2 demonstration board to test firmware. a prototype area extends the circuitry for additional application components. some of the features include an rs-232 interface, a 2 x 16 lcd display, a piezo speaker, an on-board temperature sensor, four leds and sample pic18f452 and pic16f877 flash microcontrollers. 26.18 picdem 3 pic16c92x demonstration board the picdem 3 demonstration board supports the pic16c923 and pic16c924 in the plcc package. all the necessary hardware and software is included to run the demonstration programs. 26.19 picdem 4 8/14/18-pin demonstration board the picdem 4 can be used to demonstrate the capa- bilities of the 8, 14 and 18-pin pic16xxxx and pic18xxxx mcus, including the pic16f818/819, pic16f87/88, pic16f62xa and the pic18f1320 family of microcontrollers. picdem 4 is intended to showcase the many features of these low pin count parts, including lin and motor control using eccp. special provisions are made for low-power operation with the supercapacitor circuit and jumpers allow on- board hardware to be disabled to eliminate current draw in this mode. included on the demo board are pro- visions for crystal, rc or canned oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, db-9 rs-232 interface, icd connector for programming via icsp and development with mplab icd 2, 2 x 16 liquid crystal display, pcb footprints for h-bridge motor driver, lin transceiver and eeprom. also included are: header for expansion, eight leds, four potentiometers, three push buttons and a proto- typing area. included with the kit is a pic16f627a and a pic18f1320. tutorial firmware is included along with the user?s guide. ? 2006 microchip technology inc. ds41159e-page 327 pic18fxx8 26.20 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. a pro- grammed sample is included. the pro mate ii device programmer, or the picstart plus development pro- grammer, can be used to reprogram the device for user tailored application development. the picdem 17 demonstration board supports program download and execution from external on-board flash memory. a generous prototype area is available for user hardware expansion. 26.21 picdem 18r pic18c601/801 demonstration board the picdem 18r demonstration board serves to assist development of the pic18c601/801 family of microchip microcontrollers. it provides hardware implementation of both 8-bit multiplexed/demultiplexed and 16-bit memory modes. the board includes 2 mb external flash memory and 128 kb sram memory, as well as serial eeprom, allowing access to the wide range of memory types supported by the pic18c601/801. 26.22 picdem lin pic16c43x demonstration board the powerful lin hardware and software kit includes a series of boards and three picmicro microcontrollers. the small footprint pic16c432 and pic16c433 are used as slaves in the lin communication and feature on-board lin transceivers. a pic16f874 flash microcontroller serves as the master. all three micro- controllers are programmed with firmware to provide lin bus communication. 26.23 pickit tm 1 flash starter kit a complete ?development system in a box?, the pickit? flash starter kit includes a convenient multi-section board for programming, evaluation and development of 8/14-pin flash pic ? microcontrollers. powered via usb, the board operates under a simple windows gui. the pickit 1 starter kit includes the user?s guide (on cd rom), pickit 1 tutorial software and code for various applications. also included are mplab ? ide (integrated development environment) software, software and hardware ?tips 'n tricks for 8-pin flash pic ? microcontrollers? handbook and a usb interface cable. supports all current 8/14-pin flash pic microcontrollers, as well as many future planned devices. 26.24 picdem usb pic16c7x5 demonstration board the picdem usb demonstration board shows off the capabilities of the pic16c745 and pic16c765 usb microcontrollers. this board provides the basis for future usb products. 26.25 evaluation and programming tools in addition to the picdem series of circuits, microchip has a line of evaluation kits and demonstration software for these products. ?k ee l oq evaluation and programming tools for microchip?s hcs secure data products ? can developers kit for automotive network applications ? analog design boards and filter design software ? powersmart battery charging evaluation/ calibration kits ?irda ? development kit ? microid development and rflab tm development software ? seeval ? designer kit for memory evaluation and endurance calculations ? picdem msc demo boards for switching mode power supply, high-power ir driver, delta sigma adc and flow rate sensor check the microchip web page and the latest product selector guide for the complete list of demonstration and evaluation kits. pic18fxx8 ds41159e-page 328 ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. ds41159e-page 329 pic18fxx8 27.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd , mclr and ra4) .......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) ......................................................................................... 0v to +13.25v voltage on ra4 with respect to v ss ............................................................................................................... 0v to +8.5v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) .......................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ...................................................................................................20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by all ports (combined) ................................................................................... .................200 ma maximum current sourced by all ports (combined) ................................................................................ ...............200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd ? i oh } + {(v dd ? v oh ) x i oh } + (v ol x i ol ) 2: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 should be used when applying a ?low? level to the mclr /v pp pin rather than pulling this pin directly to v ss . note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. pic18fxx8 ds41159e-page 330 ? 2006 microchip technology inc. figure 27-1: pic18fxx8 voltage-frequency graph (industrial) figure 27-2: pic18fxx8 voltage-frequency graph (extended) frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 40 mhz 5.0v 3.5v 3.0v 2.5v pic18fxx8 4.2v frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 25 mhz 5.0v 3.5v 3.0v 2.5v pic18fxx8 4.2v ? 2006 microchip technology inc. ds41159e-page 331 pic18fxx8 figure 27-3: pic18lfxx8 voltage-frequency graph (industrial) frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 40 mhz 5.0v 3.5v 3.0v 2.5v pic18lfxx8 4 mhz 4.2v f max = (16.36 mhz/v) (v ddappmin ? 2.0v) + 4 mhz, if v ddappmin 4.2v = 40 mhz, if v ddappmin > 4.2v note: v ddappmin is the minimum voltage of the picmicro ? device in the application. pic18fxx8 ds41159e-page 332 ? 2006 microchip technology inc. 27.1 dc characteristics pic18lfxx8 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18fxx8 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic/ device min typ max units conditions v dd supply voltage d001 pic18lfxx8 2.0 ? 5.5 v hs, xt, rc and lp oscillator modes d001 pic18fxx8 4.2 ? 5.5 v d002 v dr ram data retention voltage (1) 1.5 ? ? v d003 v por v dd start voltage to ensure internal power-on reset signal ? ? 0.7 v see section on power-on reset for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section on power-on reset for details v bor brown-out reset voltage pic18lfxx8 d005 borv1:borv0 = 11 1.96 ? 2.16 v borv1:borv0 = 10 2.64 ? 2.92 v borv1:borv0 = 01 4.07 ? 4.59 v borv1:borv0 = 00 4.36 ? 4.92 v pic18fxx8 d005 borv1:borv0 = 1x n.a. ? n.a. v not in operating voltage range of device borv1:borv0 = 01 4.07 ? 4.59 v borv1:borv0 = 00 4.36 ? 4.92 v legend: rows are shaded for improved readability. note 1: this is the limit to which v dd can be lowered in sleep mode, or during a device reset, without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd and v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, ...). 4: for rc oscillator configuration, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2 r ext (ma) with r ext in kohm. 5: the lvd and bor modules share a large portion of circuitry. the i bor and i lvd currents are not additive. once one of these modules is enabled, the other may also be enabled without further penalty. ? 2006 microchip technology inc. ds41159e-page 333 pic18fxx8 i dd supply current (2,3,4) d010 pic18lfxx8 ? ? ? ? ? ? ? ? ? .7 .7 1.7 1 1 2.5 .7 .7 1.8 2 2 4 2.5 2.5 5 2.5 2.5 4 ma ma ma ma ma ma ma ma ma xt oscillator configuration v dd = 2.0v, +25c, f osc = 4 mhz v dd = 2.0v, -40c to +85c, f osc = 4 mhz v dd = 4.2v, -40c to +85c, f osc = 4 mhz rc oscillator configuration v dd = 2.0v, +25c, f osc = 4 mhz v dd = 2.0v, -40c to +85c, f osc = 4 mhz v dd = 4.2v, -40c to +85c, f osc = 4 mhz rcio oscillator configuration v dd = 2.0v, +25c, f osc = 4 mhz v dd = 2.0v, -40c to +85c, f osc = 4 mhz v dd = 4.2v, -40c to +85c, f osc = 4 mhz d010 pic18fxx8 ? ? ? ? ? ? ? ? ? 1.7 1.7 1.7 2.5 2.5 2.5 1.8 1.8 1.8 4 4 4 5 5 6 4 5 5 ma ma ma ma ma ma ma ma ma xt oscillator configuration v dd = 4.2v, +25c, f osc = 4 mhz v dd = 4.2v, -40c to +85c, f osc = 4 mhz v dd = 4.2v, -40c to +125c, f osc = 4 mhz rc oscillator configuration v dd = 4.2v, +25c, f osc = 4 mhz v dd = 4.2v, -40c to +85c, f osc = 4 mhz v dd = 4.2v, -40c to +125c, f osc = 4 mhz rcio oscillator configuration v dd = 4.2v, +25c, f osc = 4 mhz v dd = 4.2v, -40c to +85c, f osc = 4 mhz v dd = 4.2v, -40c to +125c, f osc = 4 mhz d010a pic18lfxx8 ?1840 a lp oscillator, f osc = 32 khz, wdt disabled v dd = 2.0v, -40c to +85c d010a pic18fxx8 ? ? 60 60 150 180 a a lp oscillator, f osc = 32 khz, wdt disabled v dd = 4.2v, -40c to +85c v dd = 4.2v, -40c to +125c 27.1 dc characteristics (continued) pic18lfxx8 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18fxx8 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic/ device min typ max units conditions legend: rows are shaded for improved readability. note 1: this is the limit to which v dd can be lowered in sleep mode, or during a device reset, without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd and v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, ...). 4: for rc oscillator configuration, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2 r ext (ma) with r ext in kohm. 5: the lvd and bor modules share a large portion of circuitry. the i bor and i lvd currents are not additive. once one of these modules is enabled, the other may also be enabled without further penalty. pic18fxx8 ds41159e-page 334 ? 2006 microchip technology inc. i dd supply current (2,3,4) d010c pic18lfxx8 ?2128ma ec, ecio oscillator configurations v dd = 4.2v, -40c to +85c d010c pic18fxx8 ? 21 30 ma ec, ecio oscillator configurations v dd = 4.2v, -40c to +125c, f osc = 25 mhz d013 pic18lfxx8 ? ? ? 1.3 18 28 3 28 40 ma ma ma hs oscillator configurations f osc = 6 mhz, v dd = 2.0v f osc = 25 mhz, v dd = 5.5v hs + pll osc configuration f osc = 10 mhz, v dd = 5.5v d013 pic18fxx8 ? ? 18 28 28 40 ma ma hs oscillator configurations f osc = 25 mhz, v dd = 5.5v hs + pll osc configuration f osc = 10 mhz, v dd = 5.5v d014 pic18lfxx8 ?3265 a timer1 oscillator configuration f osc = 32 khz, v dd = 2.0v d014 pic18fxx8 ? ? 62 62 250 310 a a timer1 oscillator configuration f osc = 32 khz, v dd = 4.2v, -40c to +85c f osc = 32 khz, v dd = 4.2v, -40c to +125c i pd power-down current (3) d020 pic18lfxx8 ? ? 0.3 2 4 10 a a v dd = 2.0v, -40 c to +85 c v dd = 4.2v, -40 c to +85 c d020 pic18fxx8 ? 2 10 a v dd = 4.2v, -40 c to +85 c d021b ? 6 40 a v dd = 4.2v, -40 c to +125 c 27.1 dc characteristics (continued) pic18lfxx8 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18fxx8 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic/ device min typ max units conditions legend: rows are shaded for improved readability. note 1: this is the limit to which v dd can be lowered in sleep mode, or during a device reset, without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd and v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, ...). 4: for rc oscillator configuration, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2 r ext (ma) with r ext in kohm. 5: the lvd and bor modules share a large portion of circuitry. the i bor and i lvd currents are not additive. once one of these modules is enabled, the other may also be enabled without further penalty. ? 2006 microchip technology inc. ds41159e-page 335 pic18fxx8 i wdt module differential current d022 watchdog timer pic18lfxx8 ? ? ? 0.75 0.8 7 1.5 8 25 a a a v dd = 2.5v, +25 c v dd = 2.0v, -40 c to +85 c v dd = 4.2v, -40 c to +85 c d022 watchdog timer pic18fxx8 ? ? ? 7 7 7 25 25 45 a a a v dd = 4.2v, +25 c v dd = 4.2v, -40 c to +85 c v dd = 4.2v, -40 c to +125 c d022a i bor brown-out reset (5) pic18lfxx8 ? ? ? 38 42 49 50 55 65 a a a v dd = 2.0v, +25 c v dd = 2.0v, -40 c to +85 c v dd = 4.2v, -40 c to +85 c d022a brown-out reset (5) pic18fxx8 ? ? ? 46 49 50 65 65 75 a a a v dd = 4.2v, +25 c v dd = 4.2v, -40 c to +85 c v dd = 4.2v, -40 c to +125 c d022b i lvd low-voltage detect (5) pic18lfxx8 ? ? ? 36 40 47 50 55 65 a a a v dd = 2.0v, +25 c v dd = 2.0v, -40 c to +85 c v dd = 4.2v, -40 c to +85 c d022b low-voltage detect (5) pic18fxx8 ? ? ? 44 47 47 65 65 75 a a a v dd = 4.2v, +25 c v dd = 4.2v, -40 c to +85 c v dd = 4.2v, -40 c to +125 c d025 i tmr 1 timer1 oscillator pic18lfxx8 ? ? ? 6.2 6.2 7.5 40 45 55 a a a v dd = 2.0v, +25 c v dd = 2.0v, -40 c to +85 c v dd = 4.2v, -40 c to +85 c d025 timer1 oscillator pic18fxx8 ? ? ? 7.5 7.5 7.5 55 55 65 a a a v dd = 4.2v, +25 c v dd = 4.2v, -40 c to +85 c v dd = 4.2v, -40 c to +125 c 27.1 dc characteristics (continued) pic18lfxx8 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18fxx8 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic/ device min typ max units conditions legend: rows are shaded for improved readability. note 1: this is the limit to which v dd can be lowered in sleep mode, or during a device reset, without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd and v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, ...). 4: for rc oscillator configuration, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2 r ext (ma) with r ext in kohm. 5: the lvd and bor modules share a large portion of circuitry. the i bor and i lvd currents are not additive. once one of these modules is enabled, the other may also be enabled without further penalty. pic18fxx8 ds41159e-page 336 ? 2006 microchip technology inc. 27.2 dc characteristics: pic18fxx8 (industrial, extended) pic18lfxx8 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic/ device min max units conditions v il input low voltage i/o ports: d030 with ttl buffer v ss 0.15 v dd vv dd < 4.5v d030a ? 0.8 v 4.5v v dd 5.5v d031 with schmitt trigger buffer rc3 and rc4 v ss v ss 0.2 v dd 0.3 v dd v v d032 mclr v ss 0.2 v dd v d032a osc1 (in xt, hs and lp modes) and t1osi v ss 0.3 v dd v d033 osc1 (in rc mode) (1) v ss 0.2 v dd v v ih input high voltage i/o ports: d040 with ttl buffer 0.25 v dd + 0.8v v dd vv dd < 4.5v d040a 2.0 v dd v4.5v v dd 5.5v d041 with schmitt trigger buffer rc3 and rc4 0.8 v dd 0.7 v dd v dd v dd v v d042 mclr 0.8 v dd v dd v d042a osc1 (in xt, hs and lp modes) and t1osi 0.7 v dd v dd v d043 osc1 (rc mode) (1) 0.9 v dd v dd v i il input leakage current (2,3) d060 i/o ports ? 1 av ss v pin v dd , pin at high-impedance d061 mclr ? 5 a vss v pin v dd d063 osc1 ? 5 a vss v pin v dd i pu weak pull-up current d070 i purb portb weak pull-up current 50 450 av dd = 5v, v pin = v ss note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the picmicro ? device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. ? 2006 microchip technology inc. ds41159e-page 337 pic18fxx8 v ol output low voltage d080 i/o ports ? 0.6 v i ol = 8.5 ma, v dd = 4.2v, -40 c to +85 c d080a ? 0.6 v i ol = 7.0 ma, v dd = 4.2v, -40 c to +125 c d083 osc2/clko (rc mode) ?0.6vi ol = 1.6 ma, v dd = 4.2v, -40 c to +85 c d083a ? 0.6 v i ol = 1.2 ma, v dd = 4.2v, -40 c to +125 c v oh output high voltage (3) d090 i/o ports v dd ? 0.7 ? v i oh = -3.0 ma, v dd = 4.2v, -40 c to +85 c d090a v dd ? 0.7 ? v i oh = -2.5 ma, v dd = 4.2v, -40 c to +125 c d092 osc2/clko (rc mode) v dd ? 0.7 ? v i oh = -1.3 ma, v dd = 4.2v, -40 c to +85 c d092a v dd ? 0.7 ? v i oh = -1.0 ma, v dd = 4.2v, -40 c to +125 c d150 v od open-drain high voltage ? 7.5 v ra4 pin capacitive loading specs on output pins d101 c io all i/o pins and osc2 (in rc mode) ? 50 pf to meet the ac timing specifications d102 c b scl, sda ? 400 pf in i 2 c? mode 27.2 dc characteristics: pic18fxx8 (industrial, extended) pic18lfxx8 (industrial) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic/ device min max units conditions note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the picmicro ? device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. pic18fxx8 ds41159e-page 338 ? 2006 microchip technology inc. figure 27-4: low-voltage detect characteristics table 27-1: low-voltage detect characteristics v lvd lvdif v dd (lvdif set by hardware) (lvdif can be cleared in software) 37 low-voltage detect characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ max units conditions d420 v lvd lvd voltage lvv = 0001 1.96 2.06 2.16 v t 25c lvv = 0010 2.16 2.27 2.38 v t 25c lvv = 0011 2.35 2.47 2.59 v t 25c lvv = 0100 2.43 2.58 2.69 v lvv = 0101 2.64 2.78 2.92 v lvv = 0110 2.75 2.89 3.03 v lvv = 0111 2.95 3.1 3.26 v lvv = 1000 3.24 3.41 3.58 v lvv = 1001 3.43 3.61 3.79 v lvv = 1010 3.53 3.72 3.91 v lvv = 1011 3.72 3.92 4.12 v lvv = 1100 3.92 4.13 4.34 v lvv = 1101 4.07 4.33 4.59 v lvv = 1110 4.36 4.64 4.92 v ? 2006 microchip technology inc. ds41159e-page 339 pic18fxx8 table 27-2: dc characteristics: eeprom and enhanced flash dc characteristics standard operating conditions param no. sym characteristic min typ? max units conditions internal program memory programming specifications d110 v pp voltage on mclr /v pp pin 9.00 ? 13.25 v d113 i ddp supply current during programming ??10ma data eeprom memory d120 e d cell endurance 100k 1m ? e/w -40c to +85c d120a e d byte endurance 10k 100k ? e/w +85c to +125c d121 v drw v dd for read/write v min ? 5.5 v using eecon to read/write v min = minimum operating voltage d122 t dew erase/write cycle time ? 4 ? ms d123 t retd characteristic retention 40 ? ? year provided no other specifications are violated d124 t ref number of total erase/write cycles to data eeprom before refresh* 1m 10m ? cycles -40c to +85c d124a t ref number of total erase/write cycles before refresh* 100k 1m ? cycles +85c to +125c program flash memory d130 e p cell endurance 10k 100k ? e/w -40c to +85c d130a e p cell endurance 1000 10k ? e/w +85c to +125c d131 v pr v dd for read v min ?5.5vv min = minimum operating voltage d132 v ie v dd for block erase 4.5 ? 5.5 v using icsp? port d132a v iw v dd for externally timed erase or write 4.5 ? 5.5 v using icsp port d132b v pew v dd for self-timed write v min ?5.5vv min = minimum operating voltage d133 t ie icsp erase cycle time ? 4 ? ms v dd 4.5v d133a t iw icsp erase or write cycle time (externally timed) 1??msv dd 4.5v d133a t iw self-timed write cycle time ? 2 ? ms d134 t retd characteristic retention 40 ? ? year provided no other specifications are violated ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. * see section 5.8 ?using the data eeprom? for more information. pic18fxx8 ds41159e-page 340 ? 2006 microchip technology inc. table 27-3: comparator specifications table 27-4: voltage reference specifications operating conditions: v dd range as described in section 27.1 ?dc characteristics? , -40 c < t a < +125 c param no. sym characteristics min typ max units comments d300 v ioff input offset voltage ? 5.0 10 mv d301 v icm input common mode voltage 0 ? v dd ? 1.5 v d302 cmrr cmrr +55* ? ? db d300 t resp response time (1) ? 300* 350* 400* 600* ns ns pic18fxx8 pic18lfxx8 d301 t mc 2 ov comparator mode change to output valid ?? 10* s * these parameters are characterized but not tested. note 1: response time measured with one comparator input at (v dd ? 1.5)/2 while the other input transitions from v ss to v dd . operating conditions: v dd range as described in section 27.1 ?dc characteristics? , -40 c < t a < +125 c param no. sym characteristics min typ max units comments d310 v res resolution v dd /24 ? v dd /32 lsb d311 v raa absolute accuracy ? ? 0.5 lsb d312 v rur unit resistor value (r) ? 2k* ? d310 t set settling time (1) ?? 10* s * these parameters are characterized but not tested. note 1: settling time measured while cvrr = 1 and cvr<3:0> transitions from 0000 to 1111 . ? 2006 microchip technology inc. ds41159e-page 341 pic18fxx8 27.3 ac (timing) characteristics 27.3.1 timing parameter symbology the timing parameter symbols have been created using one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clko rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impedance) v valid l low z high-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition pic18fxx8 ds41159e-page 342 ? 2006 microchip technology inc. 27.3.2 timing conditions the temperature and voltages specified in table 27-5 apply to all timing specifications unless otherwise noted. figure 27-5 specifies the load conditions for the timing specifications. table 27-5: temperature and voltage specifications ? ac figure 27-5: load conditions for devi ce timing specifications ac characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in dc specification, section 27.1 ?dc characteristics? . lf parts operate for industrial temperatures only. v dd /2 c l r l pin pin v ss v ss c l r l = 464 c l = 50 pf for all pins except osc2/clko and including d and e outputs as ports load condition 1 load condition 2 ? 2006 microchip technology inc. ds41159e-page 343 pic18fxx8 27.3.3 timing diagrams and specifications figure 27-6: external clock timing table 27-6: external clock timing requirements osc1 clko q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 param no. symbol characteristic min max units conditions 1a f osc external clki frequency (1) oscillator frequency (1) dc 40 mhz ec, ecio oscillator, -40c to +85c dc 25 mhz ec, ecio oscillator, +85c to +125c dc 4 mhz rc oscillator 0.1 4 mhz xt oscillator 4 25 mhz hs oscillator, -40c to +85c 4 25 mhz hs oscillator, +85c to +125c 4 10 mhz hs + pll oscillator, -40c to +85c 4 6.25 mhz hs + pll oscillator, +85c to +125c dc 200 khz lp oscillator 1t osc external clki period (1) oscillator period (1) 25 ? ns ec, ecio oscillator, -40c to +85c 40 ? ns ec, ecio oscillator, +85c to +125c 250 ? ns rc oscillator 250 10,000 ns xt oscillator 40 ? ns hs oscillator, -40c to +85c 40 ? ns hs oscillator, +85c to +125c 100 250 ns hs + pll oscillator, -40c to +85c 160 250 ns hs + pll oscillator, +85c to +125c 5 200 s lp oscillator 2t cy instruction cycle time (1) 100 160 ? ? ns ns t cy = 4/f osc , -40c to +85c t cy = 4/f osc , +85c to +125c 3 tosl, to sh external clock in (osc1) high or low time 30 ? ns xt oscillator 2.5 ? ns lp oscillator 10 ? s hs oscillator 4tosr, to sf external clock in (osc1) rise or fall time ? 20 ns xt oscillator ? 50 ns lp oscillator ? 7.5 ns hs oscillator note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clki pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices. pic18fxx8 ds41159e-page 344 ? 2006 microchip technology inc. table 27-7: pll clock timing specifications (v dd = 4.2 to 5.5v) figure 27-7: clko and i/o timing table 27-8: clko and i/o timing requirements param no. sym characteristic min typ? max units conditions ?f osc oscillator frequency range 4 ? 10 mhz hs mode only ?f sys on-chip vco system frequency 16 ? 40 mhz hs mode only ?t rc pll start-up time (lock time) ? ? 2 ms ? clk clko stability (jitter) -2 ? +2 % ? data in ?typ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. param no. symbol characteristic min typ max units conditions 10 tosh2ckl osc1 to clko ?75200ns (1) 11 tosh2ckh osc1 to clko ?75200ns (1) 12 tckr clko rise time ? 35 100 ns (1) 13 tckf clko fall time ? 35 100 ns (1) 14 tckl2iov clko to port out valid ? ? 0.5 t cy + 20 ns (1) 15 tiov2ckh port in valid before clko 0.25 t cy + 25 ? ? ns (1) 16 tckh2ioi port in hold after clko 0??ns (1) 17 tosh2iov osc1 (q1 cycle) to port out valid ? 50 150 ns 18 tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) pic18 f xx8 100 ? ? ns 18a pic18 lf xx8 200 ? ? ns 19 tiov2osh port input valid to osc1 (i/o in setup time) 0 ? ? ns 20 t io r port output rise time pic18 f xx8 ? 10 25 ns 20a pic18 lf xx8 ? ? 60 ns 21 t io f port output fall time pic18 f xx8 ? 10 25 ns 21a pic18 lf xx8 ? ? 60 ns 22? t inp int pin high or low time t cy ??ns 23? t rbp rb7:rb4 change int high or low time t cy ??ns 24? t rcp rc7:rc4 change int high or low time 20 ? ? ns ? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode where clko pin output is 4 x t osc . note: refer to figure 27-5 for load conditions. osc1 clko i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value ? 2006 microchip technology inc. ds41159e-page 345 pic18fxx8 figure 27-8: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 27-9: brown-out reset and low-voltage detect timing table 27-9: reset, watchdog timer, oscillator start-up timer, power-up timer, brown-out reset and low-voltage detect requirements param no. symbol characteristic min typ max units conditions 30 tmcl mclr pulse width (low) 2 ? ? s 31 t wdt watchdog timer time-out period (no prescaler) 71833ms 32 t ost oscillation start-up timer period 1024 t osc ? 1024 t osc ?t osc = osc1 period 33 t pwrt power-up timer period 28 72 132 ms 34 t ioz i/o high-impedance from mclr low or watchdog timer reset ?2? s 35 t bor brown-out reset pulse width 200 ? ? sfor v dd bv dd (see d005) 36 t irvst time for internal reference voltage to become stable ?2050 s 37 t lvd low-voltage detect pulse width 200 ? ? sfor v dd v lvd (see d420) v dd mclr internal por pwrt time-out oscillator time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 27-5 for load conditions. v dd bv dd (for 35) 35, 37 v bgap = 1.2v v irvst enable internal internal reference 36 v lvd (for 37) reference voltage voltage stable pic18fxx8 ds41159e-page 346 ? 2006 microchip technology inc. figure 27-10: timer0 and timer1 external clock timings table 27-10: timer0 and timer1 external clock requirements param no. symbol characteristic min max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 41 tt0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 42 tt0p t0cki period no prescaler t cy + 10 ? ns with prescaler greater of: 20 ns or t cy + 40 n ? ns n = prescale value (1, 2, 4,..., 256) 45 tt1h t1cki high time synchronous, no prescaler 0.5 t cy + 20 ? ns synchronous, with prescaler pic18 f xx8 10 ? ns pic18 lf xx8 25 ? ns asynchronous pic18 f xx8 30 ? ns pic18 lf xx8 50 ? ns 46 tt1l t1cki low time synchronous, no prescaler 0.5 t cy + 5 ? ns synchronous, with prescaler pic18 f xx8 10 ? ns pic18 lf xx8 25 ? ns asynchronous pic18 f xx8 30 ? ns pic18 lf xx8 tbd tbd ns 47 tt1p t1cki input period synchronous greater of: 20 ns or t cy + 40 n ? ns n = prescale value (1, 2, 4, 8) asynchronous 60 ? ns ft1 t1cki oscillator input frequency range dc 50 khz 48 tcke2tmri delay from external t1cki clock edge to timer increment 2 t osc 7 t osc ? legend: tbd = to be determined note: refer to figure 27-5 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t1cki tmr0 or tmr1 ? 2006 microchip technology inc. ds41159e-page 347 pic18fxx8 figure 27-11: capture/compare/pwm timings (ccp1 and eccp1) table 27-11: capture/compare/pwm requirements (ccp1 and eccp1) note: refer to figure 27-5 for load conditions. ccpx (capture mode) 50 51 52 ccpx 53 54 (compare or pwm mode) param no. symbol characteristic min max units conditions 50 tccl ccpx input low time no prescaler 0.5 t cy + 20 ? ns with prescaler pic18 f xx8 10 ? ns pic18 lf xx8 20 ? ns 51 tcch ccpx input high time no prescaler 0.5 t cy + 20 ? ns with prescaler pic18 f xx8 10 ? ns pic18 lf xx8 20 ? ns 52 tccp ccpx input period 3 t cy + 40 n ?nsn = prescale value (1, 4 or 16) 53 tccr ccpx output fall time pic18 f xx8 ? 25 ns pic18 lf xx8 ? 45 ns 54 tccf ccpx output fall time pic18 f xx8 ? 25 ns pic18 lf xx8 ? 45 ns pic18fxx8 ds41159e-page 348 ? 2006 microchip technology inc. figure 27-12: parallel slave port timing (pic18f248 and pic18f458) table 27-12: parallel slave port requirements (pic18f248 and pic18f458) note: refer to figure 27-5 for load conditions. re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65 param no. symbol characteristic min max units conditions 62 tdtv2wrh data-in valid before wr or cs (setup time) 20 25 ? ? ns ns extended temp. range 63 twrh2dti wr or cs to data-in invalid (hold time) pic18 f xx8 20 ? ns pic18 lf xx8 35 ? ns 64 trdl2dtv rd and cs to data-out valid ? ? 80 90 ns ns extended temp. range 65 trdh2dti rd or cs to data-out invalid 10 30 ns 66 tibfinh inhibit the ibf flag bit being cleared from wr or cs ?3 t cy ns ? 2006 microchip technology inc. ds41159e-page 349 pic18fxx8 figure 27-13: example spi? master mode timing (cke = 0 ) table 27-13: example spi? mode requirements (master mode, cke = 0 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit 6 - - - - - -1 msb in lsb in bit 6 - - - -1 note: refer to figure 27-5 for load conditions. param no. symbol characteristic min max units conditions 70 tssl2sch, tss l2 s cl ss to sck or sck input t cy ?ns 71 tsch sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18 f xx8 ? 25 ns pic18 lf xx8 ? 45 ns 76 tdof sdo data output fall time ? 25 ns 78 tscr sck output rise time (master mode) pic18 f xx8 ? 25 ns pic18 lf xx8 ? 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18 f xx8 ? 50 ns pic18 lf xx8 ? 100 ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. pic18fxx8 ds41159e-page 350 ? 2006 microchip technology inc. figure 27-14: example spi? master mode timing (cke = 1 ) table 27-14: example spi? mode requirements (master mode, cke = 1 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit 6 - - - - - -1 lsb in bit 6 - - - -1 lsb note: refer to figure 27-5 for load conditions. param no. symbol characteristic min max units conditions 71 tsch sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18 f xx8 ? 25 ns pic18 lf xx8 ? 45 ns 76 tdof sdo data output fall time ? 25 ns 78 tscr sck output rise time (master mode) pic18 f xx8 ? 25 ns pic18 lf xx8 ? 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18 f xx8 ? 50 ns pic18 lf xx8 ? 100 ns 81 tdov2sch, tdov2scl sdo data output setup to sck edge t cy ?ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ? 2006 microchip technology inc. ds41159e-page 351 pic18fxx8 figure 27-15: example spi? slave mode timing (cke = 0 ) table 27-15: example spi? mode requirements, slave mode timing (cke = 0 ) param no. symbol characteristic min max units conditions 70 tssl2sch, tssl2scl ss to sck or sck input t cy ?ns 71 tsch sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18 f xx8 ? 25 ns pic18 lf xx8 45 ns 76 tdof sdo data output fall time ? 25 ns 77 tssh2doz ss to sdo output high-impedance 10 50 ns 78 tscr sck output rise time (master mode) pic18 f xx8 ? 25 ns pic18 lf xx8 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18 f xx8 ? 50 ns pic18 lf xx8 100 ns 83 tsch2ssh, ts c l 2 s s h ss after sck edge 1.5 t cy + 40 ? ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 msb lsb bit 6 - - - - - -1 bit 6 - - - -1 lsb in 83 note: refer to figure 27-5 for load conditions. msb in pic18fxx8 ds41159e-page 352 ? 2006 microchip technology inc. figure 27-16: example spi? slave mode timing (cke = 1 ) table 27-16: example spi? slave mode requirements (cke = 1 ) param no. symbol characteristic min max units conditions 70 tssl2sch, tssl2scl ss to sck or sck input t cy ?ns 71 tsch sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18 f xx8 ? 25 ns pic18 lf xx8 ? 45 ns 76 tdof sdo data output fall time ? 25 ns 77 tssh2doz ss to sdo output high-impedance 10 50 ns 78 tscr sck output rise time (master mode) pic18 f xx8 ? 25 ns pic18 lf xx8 ? 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18 f xx8 ? 50 ns pic18 lf xx8 ? 100 ns 82 tssl2dov sdo data output valid after ss edge pic18 f xx8 ? 50 ns pic18 lf xx8 ? 100 ns 83 tsch2ssh, tscl2ssh ss after sck edge 1.5 t cy + 40 ? ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 71 72 82 74 75, 76 msb bit 6 - - - - - -1 lsb 77 msb in bit 6 - - - -1 lsb in 80 83 note: refer to figure 27-5 for load conditions. 70 ? 2006 microchip technology inc. ds41159e-page 353 pic18fxx8 figure 27-17: i 2 c? bus start/stop bits timing table 27-17: i 2 c? bus start/stop bits requirements (slave mode) figure 27-18: i 2 c? bus data timing note: refer to figure 27-5 for load conditions. 91 92 93 scl sda start condition stop condition 90 param no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 4700 ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? 91 t hd : sta start condition 100 khz mode 4000 ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? 92 t su : sto stop condition 100 khz mode 4700 ? ns setup time 400 khz mode 600 ? 93 t hd : sto stop condition 100 khz mode 4000 ? ns hold time 400 khz mode 600 ? note: refer to figure 27-5 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out pic18fxx8 ds41159e-page 354 ? 2006 microchip technology inc. table 27-18: i 2 c? bus data requirements (slave mode) param no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 ? s pic18fxx8 must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s pic18fxx8 must operate at a minimum of 10 mhz ssp module 1.5 t cy ? 101 t low clock low time 100 khz mode 4.7 ? s pic18fxx8 must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s pic18fxx8 must operate at a minimum of 10 mhz ssp module 1.5 t cy ?ns 102 t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode ? 300 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 91 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period the first clock pulse is generated 400 khz mode 0.6 ? s 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 s 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92 t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 109 t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns 110 t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s d102 c b bus capacitive loading ? 400 pf note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode i 2 c? bus device can be used in a standard mode i 2 c bus system, but the requirement t su ; dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line. before the scl line is released, t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification). ? 2006 microchip technology inc. ds41159e-page 355 pic18fxx8 figure 27-19: master ssp i 2 c? bus start/stop bits timing waveforms table 27-19: master ssp i 2 c? bus start/stop bits requirements figure 27-20: master ssp i 2 c? bus data timing note: refer to figure 27-5 for load conditions. 91 93 scl sda start condition stop condition 90 92 param no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns only relevant for repeated start condition setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 91 t hd : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns after this period, the first clock pulse is generated hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 92 t su : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 93 t hd : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? note 1: maximum pin capacitance = 10 pf for all i 2 c? pins. note: refer to figure 27-5 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out pic18fxx8 ds41159e-page 356 ? 2006 microchip technology inc. table 27-20: master ssp i 2 c? bus data requirements param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 101 t low clock low time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 102 t r sda and scl rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 300 ns 103 t f sda and scl fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 100 ns 90 t su : sta start condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms only relevant for repeated start condition 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 91 t hd : sta start condition hold time 100 khz mode 2(t osc )(brg + 1) ? ms after this period, the first clock pulse is generated 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode ( 1 ) 2(t osc )(brg + 1) ? ms 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ms 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92 t su : sto stop condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 109 t aa output valid from clock 100 khz mode ? 3500 ns 400 khz mode ? 1000 ns 1 mhz mode (1) ??ns 110 t buf bus free time 100 khz mode 4.7 ? ms time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ms d102 c b bus capacitive loading ? 400 pf note 1: maximum pin capacitance = 10 pf for all i 2 c? pins. 2: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but parameter #107 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of t he scl signal, it must output the next data bit to the sda line. before the scl line is released, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 khz mode). ? 2006 microchip technology inc. ds41159e-page 357 pic18fxx8 figure 27-21: usart synchronous transmission (master/slave) timing table 27-21: usart synchronous transmission requirements figure 27-22: usart synchronous receive (master/slave) timing table 27-22: usart synchronous receive requirements note: refer to figure 27-5 for load conditions. 121 121 120 122 rc6/tx/ck rc7/rx/dt pin pin param no. symbol characteristic min max units conditions 120 tckh2dtv sync xmit (m aster & s lave ) clock high to data-out valid pic18 f xx8 ? 50 ns pic18 lf xx8 ? 150 ns 121 tckrf clock out rise time and fall time (master mode) pic18 f xx8 ? 25 ns pic18 lf xx8 ? 60 ns 122 tdtrf data-out rise time and fall time pic18 f xx8 ? 25 ns pic18 lf xx8 ? 60 ns note: refer to figure 27-5 for load conditions. 125 126 rc6/tx/ck rc7/rx/dt pin pin param no. symbol characteristic min max units conditions 125 tdtv2ckl sync rcv (m aster & s lave ) data-hold before ck (dt hold time) 10 ? ns 126 tckl2dtl data-hold after ck (dt hold time) 15 ? ns pic18fxx8 ds41159e-page 358 ? 2006 microchip technology inc. table 27-23: a/d converter characteristics: pic18fxx8 (industrial, extended) pic18lfxx8 (industrial) param no. symbol characteristic min typ max units conditions a01 n r resolution ? ? 10 bit v ref = v dd 3.0v a03 e il integral linearity error ? ? <1 lsb v ref = v dd 3.0v a04 e dl differential linearity error ? ? <1 lsb v ref = v dd 3.0v a05 e fs full scale error ? ? <1 lsb v ref = v dd 3.0v a06 e off offset error ? ? <1.5 lsb v ref = v dd 3.0v a10 ? monotonicity (3) guaranteed ? v ss v ain v ref a20 v ref reference voltage (v refh ? v refl ) 0v ? ? v a20a 3v ? ? v for 10-bit resolution a21 v refh reference voltage high v ss ?v dd + 0.3v v a22 v refl reference voltage low v ss ? 0.3v ? v dd v a25 v ain analog input voltage v ss ? 0.3v ? v ref + 0.3v v a30 z ain recommended impedance of analog voltage source ? ? 10.0 k a40 i ad a/d conversion current (v dd ) pic18 f xx8 ? 180 ? a average current consumption when a/d is on (note 1) pic18 lf xx8 ? 90 ? a a50 i ref v ref input current (note 2) 0 ? ? ? 5 150 a a during v ain acquisition. based on differential of v hold to v ain . to charge c hold . during a/d conversion cycle. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current specification includes any such leakage from the a/d module. v ref current is from ra2/an2/v ref - and ra3/an3/v ref + pins or v dd and v ss pins, whichever is selected as reference input. 2: v ss v ain v ref 3: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. ? 2006 microchip technology inc. ds41159e-page 359 pic18fxx8 figure 27-23: a/d conversion timing table 27-24: a/d conversion requirements 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (note 2) 987 21 0 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns) which also disconnects the holding capacitor from the analog input. . . . . . . t cy param no. symbol characteristic min max units conditions 130 t ad a/d clock period pic18 f xx8 1.6 20 (5) st osc based, v ref 3.0v pic18 lf xx8 3.0 20 (5) st osc based, v ref full range pic18 f xx8 2.0 6.0 s a/d rc mode pic18 lf xx8 3.0 9.0 s a/d rc mode 131 t cnv conversion time (not including acquisition time) (note 1) 11 12 t ad 132 t acq acquisition time (note 3) 15 10 ? ? s s -40 c te mp +125 c 0 c te m p +125 c 135 t swc switching time from convert sample ? (note 4) 136 t amp amplifier settling time (note 2) 1? s this may be used if the ?new? input voltage has not changed by more than 1 lsb (i.e., 5 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). note 1: adres register may be read on the following t cy cycle. 2: see section 20.0 ?compatible 10-bit analog-to-digital converter (a/d) module? for minimum conditions when input voltage has changed more than 1 lsb. 3: the time for the holding capacitor to acquire the ?new? input voltage when the voltage changes full scale after the conversion (av dd to av ss or av ss to av dd ). the source impedance ( r s ) on the input channels is 50 . 4: on the next q4 cycle of the device clock. 5: the time of the a/d clock period is dependent on the device frequency and the t ad clock divider. pic18fxx8 ds41159e-page 360 ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. ds41159e-page 361 pic18fxx8 28.0 dc and ac characteristics graphs and tables ?typical? represents the mean of the distribution at 25 c. ?maximum? or ?minimum? represents (mean + 3 ) or (mean ? 3 ) respectively, where is a standard deviation, over the whole temperature range. figure 28-1: typical i dd vs. f osc over v dd (hs mode) figure 28-2: maximum i dd vs. f osc over v dd (hs mode) note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. 0 2 4 6 8 10 12 14 16 18 20 22 24 4 8 12 16 20 24 28 32 36 40 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 4 8 12 16 20 24 28 32 36 40 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) pic18fxx8 ds41159e-page 362 ? 2006 microchip technology inc. figure 28-3: typical i dd vs. f osc over v dd (hs/pll mode) figure 28-4: maximum i dd vs. f osc over v dd (hs/pll mode) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 45678910 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.2v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 45678910 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.2v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) ? 2006 microchip technology inc. ds41159e-page 363 pic18fxx8 figure 28-5: typical i dd vs. f osc over v dd (xt mode) figure 28-6: maximum i dd vs. f osc over v dd (xt mode) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.00.51.01.52.02.53.03.54.0 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) pic18fxx8 ds41159e-page 364 ? 2006 microchip technology inc. figure 28-7: typical i dd vs. f osc over v dd (lp mode) figure 28-8: maximum i dd vs. f osc over v dd (lp mode) 0 100 200 300 400 500 600 700 20 30 40 50 60 70 80 90 100 f osc (khz) i dd ( a) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0 100 200 300 400 500 600 700 800 900 20 30 40 50 60 70 80 90 100 f osc (khz) i dd ( a) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) ? 2006 microchip technology inc. ds41159e-page 365 pic18fxx8 figure 28-9: typical i dd vs. f osc over v dd (ec mode) figure 28-10: maximum i dd vs. f osc over v dd (ec mode) 0 2 4 6 8 10 12 14 16 18 20 22 24 4 8 12 16 20 24 28 32 36 40 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v 4.2v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 4 8 12 16 20 24 28 32 36 40 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.2v 3.5v 3.0v 2.5v 2.0v 4.0v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) pic18fxx8 ds41159e-page 366 ? 2006 microchip technology inc. figure 28-11: typical and maximum i dd vs. v dd (timer1 as main oscillator 32.768 khz, c1 and c2 = 47 pf) figure 28-12: average f osc vs. v dd for various values of r (rc mode, c = 20 pf, +25 c) 0 200 400 600 800 1000 1200 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i dd ( a) typ (25c) max (70c) typical: statistical mean @ 25c maximum: mean + 3 (-10c to +70c) minimum: mean ? 3 (-10c to +70c) 0 500 1,000 1,500 2,000 2,500 3,000 3,500 4,000 4,500 2.02.53.03.54.04.55.05.5 v dd (v) freq (khz) 3.3k 5.1k 10k 100k operation above 4 mhz is not recommended. ? 2006 microchip technology inc. ds41159e-page 367 pic18fxx8 figure 28-13: average f osc vs. v dd for various values of r (rc mode, c = 100 pf, +25 c) figure 28-14: average f osc vs. v dd for various values of r (rc mode, c = 300 pf, +25 c) 0 200 400 600 800 1,000 1,200 1,400 1,600 1,800 2,000 2.02.53.03.54.04.55.05.5 v dd (v) freq (khz) 3.3k 5.1k 10k 100k 0 100 200 300 400 500 600 700 800 2.02.53.03.54.04.55.05.5 v dd (v) freq (mhz) 3.3k 5.1k 10k 100k pic18fxx8 ds41159e-page 368 ? 2006 microchip technology inc. figure 28-15: i pd vs. v dd , -40 c to +125 c (sleep mode, all peripherals disabled) figure 28-16: i bor vs. v dd over temperature (bor enabled, v bor = 2.00-2.16v) 0.01 0.1 1 10 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i ( a) typ (+25c) max (+85c) max ( -40c to +125c ) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0 10 20 30 40 50 60 70 80 90 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i dd ( a) max (125c) max (85c) typ (25c) device held in reset device in sleep max (+125c) max (+85c) typ (+25c) device held in reset device in sleep typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) ? 2006 microchip technology inc. ds41159e-page 369 pic18fxx8 figure 28-17: typical and maximum i tmr1 vs. v dd over temperature (-10 c to +70 c, timer1 with oscillator, xtal = 32 khz, c1 and c2 = 47 pf) figure 28-18: typical and maximum i wdt vs. v dd over temperature (wdt enabled) 0 2 4 6 8 10 12 14 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (ua) typ (25c) max (70c) typical: statistical mean @ 25c maximum: mean + 3 (-10c to +70c) minimum: mean ? 3 (-10c to +70c) i pd ( a) max (+70c) typ (+25c) 0 10 20 30 40 50 60 70 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) max (125c) max (85c) typ (25c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) max (+125c) max (+85c) typ (+25c) pic18fxx8 ds41159e-page 370 ? 2006 microchip technology inc. figure 28-19: typical, minimum and maximum wdt period vs. v dd (-40 c to +125 c) figure 28-20: i lvd vs. v dd over temperature (lvd enabled, v lvd = 4.5 - 4.78v) 0 5 10 15 20 25 30 35 40 45 50 2.02.53.03.54.04.55.05.5 v dd (v) wdt period (ms) max (125c) max (85c) typ (25c) min (-40c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) max (+125c) max (+85c) typ (+25c) min (-40c) 0 10 20 30 40 50 60 70 80 90 2.02.53.03.54.04.55.05.5 v dd (v) i dd ( a) max (125c) typ (25c) max (125c) typ (25c) lvdif is set b y hardware lvdif can be cleared by firmware lvdif state is unknown max (+125c) max (+125c) typ (+25c) typ (+25c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) ? 2006 microchip technology inc. ds41159e-page 371 pic18fxx8 figure 28-21: typical, minimum and maximum v oh vs. i oh (v dd = 5v, -40 c to +125 c) figure 28-22: typical, minimum and maximum v oh vs. i oh (v dd = 3v, -40 c to +125 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 5 10 15 20 25 i oh (-ma) v oh (v) typ (25c) max min max typ (+25c) min 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 i oh (-ma) v oh (v) typ (25c) max min typ (+25c) min max pic18fxx8 ds41159e-page 372 ? 2006 microchip technology inc. figure 28-23: typical and maximum v ol vs. i ol (v dd = 5v, -40 c to +125 c) figure 28-24: typical and maximum v ol vs. i ol (v dd = 3v, -40 c to +125 c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 5 10 15 20 25 i ol (-ma) v ol (v) max typ (25c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) typ (+25c) max 0.0 0.5 1.0 1.5 2.0 2.5 0 5 10 15 20 25 i ol (-ma) v ol (v) max typ (25c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) typ (+25c) max ? 2006 microchip technology inc. ds41159e-page 373 pic18fxx8 figure 28-25: minimum and maximum v in vs. v dd (st input, -40 c to +125 c) figure 28-26: minimum and maximum v in vs. v dd (ttl input, -40 c to +125 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v ih max v ih min v il max v il min typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v th (max) v th (min) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) pic18fxx8 ds41159e-page 374 ? 2006 microchip technology inc. figure 28-27: minimum and maximum v in vs. v dd (i 2 c? input, -40 c to +125 c) figure 28-28: a/d nonlinearity vs. v refh (v dd = v refh , -40 c to +125 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v ih max v ih min v il max v il min typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) v il max 0 0.5 1 1.5 2 2.5 3 3.5 4 22.533.544.555.5 v dd and v refh (v) differential or integral nonlinearity (lsb) -40c 25c 85c 125c -40c +25c +85c +125c ? 2006 microchip technology inc. ds41159e-page 375 pic18fxx8 figure 28-29: a/d nonlinearity vs. v refh (v dd = 5v, -40 c to +125 c) 0 0.5 1 1.5 2 2.5 3 22.533.544.555.5 v refh (v) differential or integral nonlinearilty (lsb) max (-40c to 125c) typ (25c) typ (+25c) max (-40c to +125c) pic18fxx8 ds41159e-page 376 ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. ds41159e-page 377 pic18fxx8 29.0 packaging information 29.1 package marking information 28-lead spdip xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example pic18f258-i/sp 0610017 28-lead soic xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example pic18f248-e/so 0610017 40-lead pdip xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx yywwnnn example pic18f448-i/p 0610017 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3 e 3 e 3 e pic18fxx8 ds41159e-page 378 ? 2006 microchip technology inc. 29.1 package marking information (continued) 44-lead plcc xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example pic18f458 -i/l 0610017 44-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example pic18f448 -i/pt 0610017 3 e 3 e ? 2006 microchip technology inc. ds41159e-page 379 pic18fxx8 29.2 package details the following sections give the technical details of the packages. 28-lead skinny plastic dual in-line (sp) ? 300 mil body (pdip) note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 8.89 8.13 .430 .350 .320 eb overall row spacing 0.56 0.48 0.41 .022 .019 .016 b lower lead width 1.65 1.33 1.02 .065 .053 .040 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 35.18 34.67 34.16 1.385 1.365 1.345 d overall length 7.49 7.24 6.99 .295 .285 .275 e1 molded package width 8.26 7.87 7.62 .325 .310 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.43 3.30 3.18 .135 .130 .125 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches * units 2 1 d n e1 c eb e p l a2 b b1 a a1 notes: jedec equivalent: mo-095 drawing no. c04-070 * controlling parameter dimension d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per sid e. significant characteristic pic18fxx8 ds41159e-page 380 ? 2006 microchip technology inc. 28-lead plastic small outline (so) ? wide, 300 mil body (soic) note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging foot angle top 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 18.08 17.87 17.65 .712 .704 .695 d overall length 7.59 7.49 7.32 .299 .295 .288 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches * units 2 1 d p n b e e1 l c 45 h a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per si de. jedec equivalent: ms-013 drawing no. c04-052 significant characteristic ? 2006 microchip technology inc. ds41159e-page 381 pic18fxx8 40-lead plastic dual in-line (p) ? 600 mil body (pdip) note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 17.27 16.51 15.75 .680 .650 .620 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.27 0.76 .070 .050 .030 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.05 .135 .130 .120 l tip to seating plane 52.45 52.26 51.94 2.065 2.058 2.045 d overall length 14.22 13.84 13.46 .560 .545 .530 e1 molded package width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 4.06 3.81 3.56 .160 .150 .140 a2 molded package thickness 4.83 4.45 4.06 .190 .175 .160 a top to seating plane 2.54 .100 p pitch 40 40 n number of pins max nom min max nom min dimension limits millimeters inches * units a2 1 2 d n e1 c eb e p l b b1 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per si de. jedec equivalent: mo-011 drawing no. c04-016 significant characteristic pic18fxx8 ds41159e-page 382 ? 2006 microchip technology inc. 44-lead plastic leaded chip carrier (l) ? square (plcc) note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ch2 x 45 ch1 x 45 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.53 0.51 0.33 .021 .020 .013 b 0.81 0.74 0.66 .032 .029 .026 b1 upper lead width 0.33 0.27 0.20 .013 .011 .008 c lead thickness 11 11 n1 pins per side 16.00 15.75 14.99 .630 .620 .590 d2 footprint length 16.00 15.75 14.99 .630 .620 .590 e2 footprint width 16.66 16.59 16.51 .656 .653 .650 d1 molded package length 16.66 16.59 16.51 .656 .653 .650 e1 molded package width 17.65 17.53 17.40 .695 .690 .685 d overall length 17.65 17.53 17.40 .695 .690 .685 e overall width 0.25 0.13 0.00 .010 .005 .000 ch2 corner chamfer (others) 1.27 1.14 1.02 .050 .045 .040 ch1 corner chamfer 1 0.86 0.74 0.61 .034 .029 .024 a3 side 1 chamfer height 0.51 .020 a1 standoff a2 molded package thickness 4.57 4.39 4.19 .180 .173 .165 a overall height 1.27 .050 p pitch 44 44 n number of pins max nom min max nom min dimension limits millimeters inches * units a2 c e2 2 d d1 n #leads=n1 e e1 1 p a3 a 35 b1 b d2 a1 .145 .153 .160 3.68 3.87 4.06 .028 .035 0.71 0.89 lower lead width * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per si de. jedec equivalent: mo-047 drawing no. c04-048 significant characteristic ? 2006 microchip technology inc. ds41159e-page 383 pic18fxx8 44-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging f a a1 a2 e e1 #leads=n1 p b d1 d n 1 2 c l ch x 45 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 ref. .039 ref. f footprint (reference) units inches millimeters * dimension limits min nom max min nom max number of pins n 44 44 pitch p .031 0.80 overall height a .039 .043 .047 1.00 1.10 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle 03.5 7 03.5 7 overall width e .463 .472 .482 11.75 12.00 12.25 overall length d .463 .472 .482 11.75 12.00 12.25 molded package width e1 .390 .394 .398 9.90 10.00 10.10 molded package length d1 .390 .394 .398 9.90 10.00 10.10 pins per side n1 11 11 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .012 .015 .017 0.30 0.38 0.44 mold draft angle top 5 10 15 5 10 15 mold draft angle bottom 5 10 15 5 10 15 dimensions d and e1 do not include mold flash or protrusions. mo ld flash or protrusions shall not exceed .010" (0.254mm) per s ide. notes: jedec equivalent: ms-026 revised 07-22-05 * controlling parameter ref: reference dimension, usually without tolerance, for information purposes only. see asme y14.5m drawing no. c04-076 pic18fxx8 ds41159e-page 384 ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. ds41159e-page 385 pic18fxx8 appendix a: data sheet revision history revision a (june 2001) original data sheet for the pic18fxx8 family. revision b (may 2002) updated information on can module, device memory and register maps, i/o ports and enhanced ccp. revision c (january 2003) this revision includes the dc and ac characteristics graphs and tables (see section 28.0 ?dc and ac characteristics graphs and tables? ), section 27.0 ?electrical characteristics? have been updated and can certification information has been added. revision d (september 2004) data sheet errata (ds80134 and ds80161) issues have been addressed and corrected along with minor corrections to the data sheet text. revision e (october 2006) packaging diagrams updated. appendix b: device differences the differences between the devices listed in this data sheet are shown in table b-1. table b-1: device differences features pic18f248 pic18f258 pic18f448 pic18f458 internal program memory bytes 16k 32k 16k 32k # of single-word instructions 8192 16384 8192 16384 data memory (bytes) 768 1536 768 1536 i/o ports ports a, b, c ports a, b, c ports a, b, c, d, e ports a, b, c, d, e enhanced capture/compare/pwm modules ?? 1 1 parallel slave port no no yes yes 10-bit analog-to-digital converter 5 input channels 5 input channels 8 input channels 8 input channels analog comparators no no 2 2 analog comparators v ref output n/a n/a yes yes packages 28-pin spdip 28-pin soic 28-pin spdip 28-pin soic 40-pin pdip 44-pin plcc 44-pin tqfp 40-pin pdip 44-pin plcc 44-pin tqfp pic18fxx8 ds41159e-page 386 ? 2006 microchip technology inc. appendix c: device migrations this section is intended to describe the functional and electrical specification differences when migrating between functionally similar devices (such as from a pic16c74a to a pic16c74b). not applicable appendix d: migrating from other picmicro ? devices this discusses some of the issues in migrating from other picmicro devices to the pic18fxx8 family of devices. d.1 pic16cxxx to pic18fxx8 see application note an716 ?migrating designs from pic16c74a/74b to pic18c442? (ds00716). d.2 pic17cxxx to pic18fxx8 see application note an726 ?pic17cxxx to pic18cxxx migration? (ds00726). ? 2006 microchip technology inc. ds41159e-page 387 pic18fxx8 index a a/d .................................................................................... 241 a/d converter flag (adif bit) .................................. 243 a/d converter interrupt, configuring ........................ 244 acquisition requirements ......................................... 244 acquisition time........................................................ 245 adcon0 register..................................................... 241 adcon1 register..................................................... 241 adresh register..................................................... 241 adresh/adresl registers ................................... 243 adresl register ..................................................... 241 analog port pins, configuring................................... 246 associated registers summary................................ 248 calculating the minimum required acquisition time ............................................... 245 configuring the module............................................. 244 conversion clock (t ad ) ............................................ 246 conversion status (go/done bit) ........................... 243 conversion t ad cycles............................................. 248 conversions .............................................................. 247 minimum charging time........................................... 245 result registers........................................................ 247 selecting the conversion clock ................................ 246 special event trigger (ccp)..................................... 126 special event trigger (eccp) .......................... 133, 248 t ad vs. device operating frequencies (for extended, lf devices) (table)................... 246 t ad vs. device operating frequencies (table) ........................................... 246 use of the eccp trigger .......................................... 248 absolute maximum ratings .............................................. 329 ac (timing) characteristics .............................................. 341 parameter symbology .............................................. 341 access bank ....................................................................... 54 ackstat ......................................................................... 173 ackstat status flag ...................................................... 173 adcon0 register............................................................. 241 go/done bit............................................................ 243 adcon1 register............................................................. 241 addlw ............................................................................. 287 addressable universal synchronous asynchronous receiver transmitter. see usart. addwf ............................................................................. 287 addwfc .......................................................................... 288 adresh register............................................................. 241 adresh/adresl registers ........................................... 243 adresl register ............................................................. 241 analog-to-digital converter. see a/d. andlw ............................................................................. 288 andwf ............................................................................. 289 assembler mpasm assembler................................................... 323 associated registers ................................................ 192, 197 b bank select register (bsr)................................................ 54 baud rate generator ........................................................ 169 bc ..................................................................................... 289 bcf ................................................................................... 290 bf ..................................................................................... 173 bf status flag .................................................................. 173 block diagrams a/d............................................................................ 243 analog input model........................................... 244, 253 baud rate generator ............................................... 169 can buffers and protocol engine ............................ 200 can receive buffer ................................................. 230 can transmit buffer ................................................ 227 capture mode operation .......................................... 125 comparator i/o operating modes ............................ 250 comparator output................................................... 252 comparator voltage reference output buffer example ..................................... 257 compare (ccp module) mode operation ................ 126 enhanced pwm........................................................ 134 interrupt logic............................................................. 78 low-voltage detect (lvd)........................................ 260 low-voltage detect with external input.................... 260 mssp (i 2 c master mode)......................................... 167 mssp (i 2 c mode)..................................................... 152 mssp (spi mode) .................................................... 143 on-chip reset circuit................................................. 25 osc2/clko/ra6 pin................................................. 94 pic18f248/258 architecture ........................................ 8 pic18f448/458 architecture ........................................ 9 pll ............................................................................. 19 portc (peripheral output override)....................... 100 portd and porte (parallel slave port)................ 107 portd in i/o port mode.......................................... 102 porte ..................................................................... 104 pwm (ccp module) ................................................. 128 ra3:ra0 and ra5 pins.............................................. 94 ra4/t0cki pin ........................................................... 94 rb1:rb0 pins............................................................. 97 rb2/cantx/int2 pin ................................................ 98 rb3/canrx pin......................................................... 98 rb7:rb4 pins............................................................. 97 reads from flash program memory .......................... 69 table read operation ................................................ 65 table write operation ................................................ 66 table writes to flash program memory ..................... 71 timer0 in 16-bit mode............................................... 110 timer0 in 8-bit mode................................................. 110 timer1 ...................................................................... 114 timer1 (16-bit read/write mode) ............................. 114 timer2 ...................................................................... 118 timer3 ...................................................................... 120 timer3 (16-bit read/write mode) ............................. 120 usart receive ....................................................... 191 usart transmit ...................................................... 189 voltage reference.................................................... 256 watchdog timer ....................................................... 273 bn..................................................................................... 290 bnc .................................................................................. 291 bnn .................................................................................. 291 bnov ............................................................................... 292 bnz .................................................................................. 292 bor. see brown-out reset. bov .................................................................................. 295 bra .................................................................................. 293 brg. see baud rate generator. brown-out reset (bor).............................................. 26, 265 pic18fxx8 ds41159e-page 388 ? 2006 microchip technology inc. bsf ................................................................................... 293 btfsc .............................................................................. 294 btfss............................................................................... 294 btg................................................................................... 295 bz...................................................................................... 296 c c compilers mplab c17 .............................................................. 324 mplab c18 .............................................................. 324 mplab c30 .............................................................. 324 call ................................................................................. 296 can module aborting transmission .............................................. 228 acknowledge error.................................................... 237 baud rate registers ................................................. 218 baud rate setting..................................................... 233 bit error..................................................................... 237 bit time partitioning (diagram) ................................. 233 bit timing configuration registers ........................... 236 brgcon1 ........................................................ 236 brgcon2 ........................................................ 236 brgcon3 ........................................................ 236 calculating t q , nominal bit rate and nominal bit time............................................... 234 configuration mode................................................... 226 control and status registers .................................... 201 controller register map ............................................ 225 crc error ................. ................................................ 237 disable mode ............................................................ 226 error detection .......................................................... 237 error modes and error counters............................... 237 error modes state (diagram) .................................... 238 error recognition mode ............................................ 227 error states............................................................... 237 filter/mask truth (table)............................................ 232 form error................................................................. 237 hard synchronization................................................ 235 i/o control register .................................................. 221 information processing time .................................... 234 initiating transmission .............................................. 228 internal message reception flowchart .......................................................... 231 internal transmit message flowchart .......................................................... 229 interrupt acknowledge .............................................. 239 interrupt registers .................................................... 222 interrupts................................................................... 238 bus activity wake-up ........................................ 239 bus-off.............................................................. 239 code bits .......................................................... 238 error .................................................................. 239 message error .................................................. 239 receive ............................................................. 238 receiver bus passive ....................................... 239 receiver overflow............................................. 239 receiver warning ............................................. 239 transmit ............................................................ 238 transmitter bus passive ................................... 239 transmitter warning ......................................... 239 lengthening a bit period (diagram)........................................................... 235 listen only mode...................................................... 226 loopback mode ........................................................ 227 message acceptance filters and masks ................................................ 215, 232 message acceptance mask and filter operation (diagram) ................................ 232 message reception .................................................. 230 message time-stamping.......................................... 230 message transmission............................................. 227 modes of operation .................................................. 226 normal mode ............................................................ 226 oscillator tolerance.................................................. 236 overview................................................................... 199 phase buffer segments............................................ 234 programming time segments .................................. 236 propagation segment ............................................... 234 receive buffer registers .......................................... 210 receive buffers ........................................................ 230 receive message buffering...................................... 230 receive priority......................................................... 230 registers .................................................................. 201 resynchronization .................................................... 235 sample point ............................................................ 234 shortening a bit period (diagram) ............................ 236 stuff bit error ............................................................ 237 synchronization ........................................................ 235 synchronization rules .............................................. 235 synchronization segment......................................... 234 time quanta ............................................................. 234 transmit buffer registers ......................................... 206 transmit buffers ....................................................... 227 transmit priority........................................................ 227 transmit/receive buffers ......................................... 199 values for icode (table).......................................... 239 capture (ccp module) ..................................................... 124 can message time-stamp ...................................... 125 ccp pin configuration.............................................. 124 ccp1 prescaler ........................................................ 125 ccpr1h:ccpr1l registers.................................... 124 software interrupt ..................................................... 125 timer1/timer3 mode selection................................. 124 capture (eccp module)................................................... 133 can message time-stamp ...................................... 133 capture/compare/pwm (ccp) ........................................ 123 capture mode. see capture (ccp module). ccp1 module ........................................................... 124 timer resources .............................................. 124 ccpr1h register..................................................... 124 ccpr1l register ..................................................... 124 compare mode. see compare (ccp module). interaction of ccp1 and eccp1 modules ............................................... 124 pwm mode. see pwm (ccp module). ceramic resonators ranges tested ........................................................... 17 clocking scheme................................................................ 41 clrf ................................................................................ 297 clrwdt .......................................................................... 297 ? 2006 microchip technology inc. ds41159e-page 389 pic18fxx8 code examples 16 x 16 signed multiply routine ................................. 76 16 x 16 unsigned multiply routine ............................. 76 8 x 8 signed multiply routine ..................................... 75 8 x 8 unsigned multiply routine ................................. 75 changing between capture prescalers.................... 125 data eeprom read .................................................. 61 data eeprom refresh routine................................. 62 data eeprom write .................................................. 61 erasing a flash program memory row ...................... 70 fast register stack..................................................... 40 how to clear ram (bank 1) using indirect addressing ............................................. 55 initializing porta....................................................... 93 initializing portb....................................................... 96 initializing portc..................................................... 100 initializing portd..................................................... 102 initializing porte..................................................... 104 loading the sspbuf register ................................. 146 reading a flash program memory word ..................................................... 69 saving status, wreg and bsr registers in ram................................................ 92 win and icode bits usage in interrupt service routine to access tx/rx buffers ...................................... 203 writing to flash program memory ........................ 72?73 code protection ................................................................ 265 comf ............................................................................... 298 comparator module .......................................................... 249 analog input connection considerations.................. 253 associated registers ................................................ 254 configuration............................................................. 250 effects of a reset...................................................... 253 external reference signal ........................................ 251 internal reference signal ......................................... 251 interrupts................................................................... 252 operation .................................................................. 251 operation during sleep ............................................ 253 outputs ..................................................................... 251 reference ................................................................. 251 response time......................................................... 251 comparator specifications................................................ 340 comparator voltage reference module ........................... 255 accuracy/error .......................................................... 256 associated registers ................................................ 257 configuring................................................................ 255 connection considerations....................................... 256 effects of a reset...................................................... 256 operation during sleep ............................................ 256 compare (ccp module) ................................................... 126 ccp1 pin configuration............................................ 126 ccpr1 and eccpr1 registers ............................... 126 registers associated with capture, compare, timer1 and timer3........................... 127 software interrupt ..................................................... 126 special event trigger........................ 115, 121, 126, 248 timer1/timer3 mode selection................................. 126 compare (eccp module) ................................................. 133 registers associated with enhanced capture, compare, timer1 and timer3 ............ 133 special event trigger................................................ 133 compatible 10-bit analog-to-digital converter (a/d) module. see a/d. configuration mode (can module) ................................... 226 cpfseq ........................................................................... 298 cpfsgt ........................................................................... 299 cpfslt ............................................................................ 299 crystal oscillator capacitor selection .................................................... 18 d data eeprom memory...................................................... 59 associated registers.................................................. 63 eeadr register......................................................... 59 eecon1 register ...................................................... 59 eecon2 register ...................................................... 59 operation during code-protect .................................. 62 protection against spurious writes ............................ 62 reading ...................................................................... 61 usage ......................................................................... 62 write verify ................................................................. 62 writing to .................................................................... 61 data memory ...................................................................... 44 general purpose registers ........................................ 44 special function registers......................................... 44 data memory map pic18f248/448 .......................................................... 45 pic18f258/458 .......................................................... 46 daw ................................................................................. 300 dc and ac characteristics graphs and tables ................................................... 361 dc characteristics............................................................ 332 eeprom and enhanced flash ................................ 339 pic18fxx8 (ind., ext.) and pic18lfxx8 (ind.) ........................................... 336 dcfsnz ........................................................................... 301 decf ................................................................................ 300 decfsz ........................................................................... 301 demonstration boards picdem 1................................................................. 326 picdem 17............................................................... 327 picdem 18r ............................................................ 327 picdem 2 plus......................................................... 326 picdem 3................................................................. 326 picdem 4................................................................. 326 picdem lin ............................................................. 327 picdem usb ........................................................... 327 picdem.net internet/ethernet.................................. 326 development support ....................................................... 323 device differences............................................................ 385 device migrations ............................................................. 386 device overview................................................................... 7 features ....................................................................... 7 direct addressing ............................................................... 56 disable mode (can module) ............................................ 226 e electrical characteristics .................................................. 329 enhanced capture/compare/pwm (eccp)..................... 131 auto-shutdown ......................................................... 142 capture mode. see capture (eccp module). compare mode. see compare (eccp module). eccpr1h register .................................................. 132 eccpr1l register................................................... 132 interaction of ccp1 and eccp1 modules ............................................... 132 pin assignments for various modes......................... 132 pwm mode. see pwm (eccp module). timer resources ...................................................... 132 pic18fxx8 ds41159e-page 390 ? 2006 microchip technology inc. enhanced ccp auto-shutdown........................................ 142 enhanced pwm mode. see pwm (eccp module). errata .................................................................................... 5 error recognition mode (can module) ............................ 226 evaluation and programming tools .................................. 327 external clock input ............................................................ 19 f firmware instructions........................................................ 281 flash program memory....................................................... 65 associated registers .................................................. 74 control registers ........................................................ 66 erase sequence ......................................................... 70 erasing ........................................................................ 70 operation during code-protect .................................. 73 reading....................................................................... 69 tablat (table latch) register.................................. 68 table pointer boundaries based on operation......................... 68 table pointer boundaries ........................................... 68 table reads and table writes ................................... 65 tblptr (table pointer) register ............................... 68 write sequence .......................................................... 71 writing to ..................................................................... 71 protection against spurious writes .................... 73 unexpected termination..................................... 73 write verify ......................................................... 73 g goto................................................................................ 302 h hardware multiplier ............................................................. 75 operation .................................................................... 75 performance comparison (table) ................................ 75 hs4 (pll) ........................................................................... 19 i i/o ports .............................................................................. 93 i 2 c mode ........................................................................... 152 ack pulse......................................................... 156, 157 acknowledge sequence timing................................ 176 baud rate generator ................................................ 169 bus collision during a repeated start condition.................................. 180 bus collision during a start condition ...................... 178 bus collision during a stop condition ...................... 181 clock arbitration........................................................ 170 clock stretching ........................................................ 162 effect of a reset ....................................................... 177 general call address support .................................. 166 master mode ............................................................. 167 operation .......................................................... 168 reception.......................................................... 173 repeated start condition timing...................... 172 start condition timing ...................................... 171 transmission..................................................... 173 multi-master mode .................................................... 177 communication, bus collision and bus arbitration ................................... 177 operation .................................................................. 156 read/write bit information (r/w bit) ................ 156, 157 registers................................................................... 152 serial clock (rc3/sck/scl).................................... 157 slave mode............................................................... 156 addressing........................................................ 156 reception ......................................................... 157 transmission .................................................... 157 sleep operation........................................................ 177 stop condition timing .............................................. 176 id locations.............................................................. 265, 279 incf ................................................................................. 302 incfsz............................................................................. 303 in-circuit debugger........................................................... 279 in-circuit serial programming (icsp)....................... 265, 279 indirect addressing ............................................................. 56 fsr register .............................................................. 55 indf register ............................................................. 55 operation .................................................................... 55 infsnz............................................................................. 303 initialization conditions for all registers............................. 30 instruction cycle ................................................................. 41 instruction flow/pipelining .................................................. 41 instruction format............................................................. 283 instruction set................................................................... 281 addlw..................................................................... 287 addwf..................................................................... 287 addwfc .................................................................. 288 andlw..................................................................... 288 andwf..................................................................... 289 bc............................................................................. 289 bcf .......................................................................... 290 bn............................................................................. 290 bnc .......................................................................... 291 bnn .......................................................................... 291 bnov ....................................................................... 292 bnz .......................................................................... 292 bov .......................................................................... 295 bra .......................................................................... 293 bsf........................................................................... 293 btfsc ...................................................................... 294 btfss ...................................................................... 294 btg .......................................................................... 295 bz ............................................................................. 296 call......................................................................... 296 clrf ........................................................................ 297 clrwdt .................................................................. 297 comf ....................................................................... 298 cpfseq ................................................................... 298 cpfsgt ................................................................... 299 cpfslt .................................................................... 299 daw ......................................................................... 300 dcfsnz ................................................................... 301 decf ........................................................................ 300 decfsz ................................................................... 301 goto ....................................................................... 302 incf ......................................................................... 302 incfsz..................................................................... 303 infsnz..................................................................... 303 iorlw ...................................................................... 304 iorwf...................................................................... 304 lfsr ........................................................................ 305 movf ....................................................................... 305 movff ..................................................................... 306 movlb ..................................................................... 306 movlw .................................................................... 307 movwf .................................................................... 307 mullw..................................................................... 308 mulwf..................................................................... 308 ? 2006 microchip technology inc. ds41159e-page 391 pic18fxx8 negf ........................................................................ 309 nop .......................................................................... 309 pop .......................................................................... 310 push ........................................................................ 310 rcall ...................................................................... 311 reset ...................................................................... 311 retfie ..................................................................... 312 retlw ..................................................................... 312 return ................................................................... 313 rlcf......................................................................... 313 rlncf ...................................................................... 314 rrcf ........................................................................ 314 rrncf ................................... .................................. 315 setf......................................................................... 315 sleep ...................................................................... 316 subfwb................................................................... 316 sublw ..................................................................... 317 subwf ..................................................................... 317 subwfb................................................................... 318 swapf ..................................................................... 318 tblrd ...................................................................... 319 tblwt...................................................................... 320 tstfsz .................................................................... 321 xorlw..................................................................... 321 xorwf..................................................................... 322 summary table......................................................... 284 intcon register rbif bit....................................................................... 96 inter-integrated circuit. see i 2 c. interrupt sources a/d conversion complete ........................................ 244 can module.............................................................. 238 capture complete (ccp).......................................... 125 compare complete (ccp)........................................ 126 interrupt-on-change (rb7:rb4) ................................. 96 tmr0 overflow ......................................................... 111 tmr1 overflow ................................................. 113, 115 tmr2 to pr2 match ................................................. 118 tmr2 to pr2 match (pwm) ............................. 117, 128 tmr3 overflow ................................................. 119, 121 interrupt-on-change (rb7:rb4) flag (rbif bit) .................................................................... 96 interrupts..................................................................... 77, 265 context saving during ................................................ 92 enable registers......................................................... 85 flag registers............................................................. 82 int .............................................................................. 92 portb interrupt-on-change ...................................... 92 priority registers......................................................... 88 tmr0 .......................................................................... 92 interrupts, flag bits a/d converter flag (adif bit) .................................. 243 ccp1 flag (ccp1if bit) ........................... 124, 125, 126 iorlw .............................................................................. 304 iorwf .............................................................................. 304 l lfsr ................................................................................. 305 listen only mode (can module) ...................................... 226 look-up tables ................................................................... 43 computed goto........................................................ 43 table reads/table writes .......................................... 43 loopback mode (can module)......................................... 226 low-voltage detect .......................................................... 259 characteristics.......................................................... 338 current consumption ............................................... 263 effects of a reset ..................................................... 263 operation.................................................................. 262 operation during sleep ............................................ 263 reference voltage set point .................................... 263 typical application.................................................... 259 low-voltage icsp programming...................................... 279 lvd. see low-voltage detect. m master synchronous serial port (mssp). see mssp. master synchronous serial port. see mssp. memory organization ......................................................... 37 data memory .............................................................. 44 internal program memory operation .......................... 37 program memory........................................................ 37 migrating from other picmicro devices ............................ 386 movf ............................................................................... 305 movff ............................................................................. 306 movlb ............................................................................. 306 movlw ............................................................................ 307 movwf ............................................................................ 307 mplab asm30 assembler, linker, librarian........................................................ 324 mplab icd 2 in-circuit debugger ................................... 325 mplab ice 2000 high-performance universal in-circuit emulator.................................... 325 mplab ice 4000 high-performance universal in-circuit emulator.................................... 325 mplab integrated development environment software .............................................. 323 mplab pm3 device programmer .................................... 325 mplink object linker/ mplib object librarian ............................................ 324 mssp ............................................................................... 143 control registers...................................................... 143 enabling spi i/o ....................................................... 147 operation.................................................................. 146 overview................................................................... 143 spi master mode...................................................... 148 spi master/slave connection................................... 147 spi mode.................................................................. 143 spi slave mode........................................................ 149 tmr2 output for clock shift............................. 117, 118 typical connection ................................................... 147 mssp. see also i 2 c mode, spi mode. mullw............................................................................. 308 mulwf............................................................................. 308 n negf................................................................................ 309 nop .................................................................................. 309 normal operation mode (can module)............................ 226 pic18fxx8 ds41159e-page 392 ? 2006 microchip technology inc. o opcode field descriptions ................................................ 282 oscillator effects of sleep mode ................................................. 23 power-up delays......................................................... 23 switching feature ....................................................... 20 system clock switch bit ............................................. 20 transitions .................................................................. 21 oscillator configurations ..................................................... 17 crystal oscillator, ceramic resonators ...................... 17 ec ............................................................................... 17 ecio ........................................................................... 17 hs ............................................................................... 17 hs4 ............................................................................. 17 lp................................................................................ 17 rc ......................................................................... 17, 18 rcio ........................................................................... 17 xt ............................................................................... 17 oscillator selection ........................................................... 265 oscillator, timer1 .............................................. 113, 115, 121 oscillator, wdt ................................................................. 272 p packaging information ...................................................... 377 details ....................................................................... 379 marking ..................................................................... 377 parallel slave port (psp) .......................................... 102, 107 associated registers ................................................ 108 portd ..................................................................... 107 psp mode select (pspmode) bit ........................... 102 re2/an7/cs /c2out ................................................ 107 pic18fxx8 voltage-frequency graph (industrial) ...................................................... 330 pic18lfxx8 voltage-frequency graph (industrial) ...................................................... 331 pickit 1 flash starter kit................................................... 327 picstart plus development programmer .............................................................. 326 pin functions mclr /v pp ................................................................... 10 osc1/clki ................................................................. 10 osc2/clko/ra6 ....................................................... 10 ra0/an0/cv ref ......................................................... 11 ra1/an1 ..................................................................... 11 ra2/an2/v ref -........................................................... 11 ra3/an3/v ref +.......................................................... 11 ra4/t0cki .................................................................. 11 ra5/an4/ss /lvdin.................................................... 11 ra6 ............................................................................. 11 rb0/int0 .................................................................... 12 rb1/int1 .................................................................... 12 rb2/cantx/int2 ....................................................... 12 rb3/canrx ............................................................... 12 rb4 ............................................................................. 12 rb5/pgm .................................................................... 12 rb6/pgc .................................................................... 12 rb7/pgd .................................................................... 12 rc0/t1oso/t1cki .................................................... 13 rc1/t1osi ................................................................. 13 rc2/ccp1 .................................................................. 13 rc3/sck/scl ............................................................ 13 rc4/sdi/sda ............................................................. 13 rc5/sdo .................................................................... 13 rc6/tx/ck ................................................................. 13 rc7/rx/dt ................................................................. 13 rd0/psp0/c1in+ ....................................................... 14 rd1/psp1/c1in- ........................................................ 14 rd2/psp2/c2in+ ....................................................... 14 rd3/psp3/c2in- ........................................................ 14 rd4/psp4/eccp1/p1a.............................................. 14 rd5/psp5/p1b .......................................................... 14 rd6/psp6/p1c .......................................................... 14 rd7/psp7/p1d .......................................................... 14 re0/an5/rd ............................................................... 15 re1/an6/wr /c1out................................................. 15 re2/an7/cs /c2out.................................................. 15 v dd ............................................................................. 15 v ss ............................................................................. 15 pinout i/o descriptions ....................................................... 10 pointer, fsrn ..................................................................... 55 pop .................................................................................. 310 por. see power-on reset. porta associated register summary ................................... 95 functions .................................................................... 95 lata register ............................................................ 93 porta register ......................................................... 93 trisa register........................................................... 93 portb associated register summary ................................... 99 functions .................................................................... 99 latb register ............................................................ 96 portb register ......................................................... 96 rb7:rb4 interrupt-on-change flag (rbif bit).................................................... 96 trisb register........................................................... 96 portc associated register summary ................................. 101 functions .................................................................. 101 latc register .......................................................... 100 portc register....................................................... 100 rc3/sck/scl pin .................................................... 157 rc7/rx/dt pin ......................................................... 185 trisc register................................................. 100, 183 portd associated register summary ................................. 103 functions .................................................................. 103 latd register .......................................................... 102 parallel slave port (psp) function........................... 102 portd register....................................................... 102 trisd register......................................................... 102 porte associated register summary ................................. 106 functions .................................................................. 106 late register .......................................................... 104 porte register ....................................................... 104 psp mode select (pspmode) bit ........................... 102 re2/an7/cs /c2out................................................ 107 trise register......................................................... 104 power-down mode. see sleep. power-on reset (por)............................................... 26, 265 mclr ......................................................................... 26 oscillator start-up timer (ost) .......................... 26, 265 pll lock time-out...................................................... 26 power-up timer (pwrt) .................................... 26, 265 time-out sequence .................................................... 27 power-up delays osc1 and osc2 pin states in sleep mode..................................................... 23 prescaler, timer0 ............................................................. 111 ? 2006 microchip technology inc. ds41159e-page 393 pic18fxx8 prescaler, timer2.............................................................. 128 pro mate ii universal device programmer .............................................................. 325 program counter pcl register............................................................... 40 pclath register ....................................................... 40 pclatu register ....................................................... 40 program memory ................................................................ 37 fast register stack..................................................... 40 instructions.................................................................. 41 two-word ........................................................... 43 map and stack for pic18f248/448............................. 37 map and stack for pic18f258/458............................. 37 push and pop instructions ....................................... 40 return address stack ................................................. 38 return stack pointer (stkptr) ................................. 38 stack full/underflow resets....................................... 40 top-of-stack access................................................... 38 program verification and code protection ........................................................ 276 associated registers summary................................ 276 configuration register protection ............................. 279 data eeprom code protection ............................... 279 program memory code protection ........................... 277 programming, device instructions .................................... 281 push ................................................................................ 310 pwm (ccp module) ......................................................... 128 ccpr1h:ccpr1l registers.................................... 128 duty cycle................................................................. 128 example frequencies/resolutions ........................... 129 period........................................................................ 128 registers associated with pwm and timer2 .............................................. 129 setup for pwm operation......................................... 129 tmr2 to pr2 match ......................................... 117, 128 pwm (eccp module) ....................................................... 134 full-bridge application example ............................... 138 full-bridge mode....................................................... 137 direction change .............................................. 138 half-bridge mode ...................................................... 136 half-bridge output mode applications example ....................................... 136 output configurations ............................................... 134 output polarity configuration.................................... 140 output relationships diagram .................................. 135 programmable dead-band delay ............................. 140 registers associated with enhanced pwm and timer2........................................................ 141 setup for pwm operation......................................... 141 standard mode ......................................................... 134 start-up considerations ............................................ 140 system implementation ............................................ 140 q q clock ............................................................................. 128 r ram. see data memory. rcall .............................................................................. 311 rcon register significance of status bits vs. initialization condition ......................................... 27 rcsta register ............................................................... 183 spen bit ................................................................... 183 receiver warning ............................................................. 239 register file ........................................................................ 44 register file summary ....................................................... 49 registers adcon0 (a/d control 0).......................................... 241 adcon1 (a/d control 1).......................................... 242 brgcon1 (baud rate control 1)............................ 218 brgcon2 (baud rate control 2)............................ 219 brgcon3 (baud rate control 3)............................ 220 cancon (can control) .......................................... 201 canstat (can status)........................................... 202 ccp1con (ccp1 control) ...................................... 123 ciocon (can i/o control)...................................... 221 cmcon (comparator control) ................................. 249 comstat (can communication status) .................................... 205 config1h (configuration 1 high)........................... 266 config2h (configuration 2 high)........................... 267 config2l (configuration 2 low) ............................ 266 config4l (configuration 4 low) ............................ 267 config5h (configuration 5 high)........................... 268 config5l (configuration 5 low) ............................ 268 config6h (configuration 6 high)........................... 269 config6l (configuration 6 low) ............................ 269 config7h (configuration 7 high)........................... 270 config7l (configuration 7 low) ............................ 270 cvrcon (comparator voltage reference control) ........................................... 255 devid1 (device id 1)............................................... 271 devid2 (device id 2)............................................... 271 eccp1con (eccp1 control).................................. 131 eccp1del (pwm delay) ........................................ 140 eccpas (enhanced capture/compare/pwm auto-shutdown control) ................................... 142 eecon1 (eeprom control 1) ............................ 60, 67 intcon (interrupt control) ........................................ 79 intcon2 (interrupt control 2) ................................... 80 intcon3 (interrupt control 3) ................................... 81 ipr1 (peripheral interrupt priority 1) .......................... 88 ipr2 (peripheral interrupt priority 2) .......................... 89 ipr3 (peripheral interrupt priority 3) .................. 90, 224 lvdcon (lvd control)............................................ 261 osccon (oscillator control)..................................... 20 pie1 (peripheral interrupt enable 1) .......................... 85 pie2 (peripheral interrupt enable 2) .......................... 86 pie3 (peripheral interrupt enable 3) .................. 87, 223 pir1 (peripheral interrupt request (flag) 1) .............................................................. 82 pir2 (peripheral interrupt request (flag) 2) .............................................................. 83 pir3 (peripheral interrupt request (flag) 3) ...................................................... 84, 222 rcon (reset control).......................................... 58, 91 rcsta (receive status and control) ...................... 184 rxb0con (receive buffer 0 control)...................... 210 rxb1con (receive buffer 1 control)...................... 211 rxbndlc (receive buffer n data length code) ........................................... 213 rxbndm (receive buffer n data field byte m)............................................ 214 rxbneidh (receive buffer n extended identifier, high byte)......................... 212 rxbneidl (receive buffer n extended identifier, low byte).......................... 213 rxbnsidh (receive buffer n standard identifier, high byte) ......................... 212 pic18fxx8 ds41159e-page 394 ? 2006 microchip technology inc. rxbnsidl (receive buffer n standard identifier, low byte)........................... 212 rxerrcnt (receive error count) .......................... 214 rxfneidh (receive acceptance filter n extended identifier, high byte) ......................... 216 rxfneidl (receive acceptance filter n extended identifier, low byte) .......................... 216 rxfnsidh (receive acceptance filter n standard identifier filter, high byte)................. 215 rxfnsidl (receive acceptance filter n standard identifier filter, low byte).................. 215 rxmneidh (receive acceptance mask n extended identifier mask, high byte)................ 217 rxmneidl (receive acceptance mask n extended identifier mask, low byte) ................ 217 rxmnsidh (receive acceptance mask n standard identifier mask, high byte) ................ 216 rxmnsidl (receive acceptance mask n standard identifier mask, low byte) ................. 217 sspcon1 (mssp control 1, i 2 c mode) .................. 154 sspcon1 (mssp control 1, spi mode) .................. 145 sspcon2 (mssp control 2, i 2 c mode) .................. 155 sspstat (mssp status, i 2 c mode)........................ 153 sspstat (mssp status, spi mode) ....................... 144 status .......................................................................... 57 stkptr (stack pointer) ............................................. 39 t0con (timer0 control)........................................... 109 t1con (timer1 control)........................................... 113 t2con (timer2 control)........................................... 117 t3con (timer3 control)........................................... 119 trise (porte direction/psp control).................... 105 txbncon (transmit buffer n control) ..................... 206 txbndlc (transmit buffer n data length code)............................................ 209 txbndm (transmit buffer n data field byte m) ............................................ 208 txbneidh (transmit buffer n extended identifier, high byte) ......................... 207 txbneidl (transmit buffer n extended identifier, low byte) .......................... 208 txbnsidh (transmit buffer n standard identifier, high byte).......................... 207 txbnsidl (transmit buffer n standard identifier, low byte)........................... 207 txerrcnt (transmit error count).......................... 209 txsta (transmit status and control) ...................... 183 wdtcon (watchdog timer control)........................ 272 reset .............................................................................. 311 reset........................................................................... 25, 265 mclr reset during normal operation ...................... 25 mclr reset during sleep.......................................... 25 power-on reset (por) ............................................... 25 programmable brown-out reset (pbor) ................... 25 reset instruction ...................................................... 25 stack full reset .......................................................... 25 stack underflow reset ............................................... 25 watchdog timer (wdt) reset.................................... 25 retfie ............................................................................. 312 retlw.............................................................................. 312 return ........................................................................... 313 revision history ................................................................ 385 rlcf................................................................................. 313 rlncf .............................................................................. 314 rrcf ................................................................................ 314 rrncf......................... ..................................................... 315 s sci. see usart. sck pin ............................................................................ 143 sdi pin.............................................................................. 143 sdo pin............................................................................ 143 serial clock (sck) pin...................................................... 143 serial communication interface. see usart. serial peripheral interface. see spi. setf................................................................................. 315 slave select (ss ) pin ....................................................... 143 slave select, ss pin......................................................... 143 sleep .............................................................................. 316 sleep......................................................................... 265, 274 software simulator (mplab sim) .................................... 324 software simulator (mplab sim30) ................................ 324 special event trigger. see compare. special features of the cpu ............................................ 265 configuration bits ..................................................... 265 configuration bits and device ids ........................................................ 265 configuration registers .................................... 266?271 special function register map........................................... 47 special function registers ................................................. 44 spi mode associated registers ................................................ 151 bus mode compatibility ............................................ 151 effects of a reset ..................................................... 151 master mode............................................................. 148 master/slave connection.......................................... 147 registers .................................................................. 144 serial clock............................................................... 143 serial data in (sdi) pin ............................................ 143 serial data out (sdo) pin........................................ 143 slave select.............................................................. 143 slave select synchronization ................................... 149 sleep operation........................................................ 151 spi clock .................................................................. 148 sspbuf register ..................................................... 148 sspsr register ....................................................... 148 sspov ............................................................................. 173 sspov status flag .......................................................... 173 sspstat register r/w bit ............................................................. 156, 157 subfwb .......................................................................... 316 sublw ............................................................................. 317 subwf............................................................................. 317 subwfb .......................................................................... 318 swapf ............................................................................. 318 t table pointer operations (table)......................................... 68 tblrd .............................................................................. 319 tblwt.............................................................................. 320 timer0............................................................................... 109 16-bit mode timer reads and writes ....................... 111 associated registers ................................................ 111 operation .................................................................. 111 overflow interrupt ..................................................... 111 prescaler .................................................................. 111 prescaler. see prescaler, timer0. switching prescaler assignment .............................. 111 ? 2006 microchip technology inc. ds41159e-page 395 pic18fxx8 timer1 ............................................................................... 113 16-bit read/write mode ............................................ 115 associated registers ................................................ 116 operation .................................................................. 114 oscillator ........................................................... 113, 115 overflow interrupt ............................................. 113, 115 special event trigger (ccp)............................. 115, 126 special event trigger (eccp) .................................. 133 tmr1h register ....................................................... 113 tmr1l register........................................................ 113 tmr3l register........................................................ 119 timer2 ............................................................................... 117 associated registers ................................................ 118 operation .................................................................. 117 postscaler. see postscaler, timer2. pr2 register..................................................... 117, 128 prescaler. see prescaler, timer2. ssp clock shift................................................. 117, 118 tmr2 register.......................................................... 117 tmr2 to pr2 match interrupt ................... 117, 118, 128 timer3 ............................................................................... 119 associated registers ................................................ 121 operation .................................................................. 120 oscillator ................................................................... 121 overflow interrupt ............................................. 119, 121 special event trigger (ccp)..................................... 121 tmr3h register ....................................................... 119 timing conditions ............................................................. 342 load conditions for device timing specifications........................................ 342 temperature and voltage specifications ? ac........................................... 342 timing diagrams a/d conversion......................................................... 359 acknowledge sequence ........................................... 176 baud rate generator with clock arbitration ............................................... 170 brg reset due to sda arbitration during start condition ...................................... 179 brown-out reset (bor) and low-voltage detect .......................................... 345 bus collision during a repeated start condition (case 1) ................................... 180 bus collision during a repeated start condition (case2) .................................... 180 bus collision during a stop condition (case 1) ............................................ 181 bus collision during a stop condition (case 2) ................................... 181 bus collision during start condition (scl = 0).................................. 179 bus collision during start condition (sda only) ............................... 178 bus collision for transmit and acknowledge .................................................... 177 capture/compare/pwm (ccp1 and eccp1) .......................................... 347 clko and i/o ........................................................... 344 clock synchronization .............................................. 163 clock/instruction cycle ............................................... 41 external clock........................................................... 343 first start bit ............................................................. 171 full-bridge pwm output ........................................... 137 half-bridge pwm output .......................................... 136 i 2 c bus data............................................................. 353 i 2 c bus start/stop bits ............................................. 353 i 2 c master mode (reception, 7-bit address) ................................................... 175 i 2 c master mode (transmission, 7 or 10-bit address) .......................................... 174 i 2 c slave mode (transmission, 10-bit address) ................................................. 161 i 2 c slave mode (transmission, 7-bit address) ................................................... 159 i 2 c slave mode with sen = 0 (reception, 10-bit address) ................................................. 160 i 2 c slave mode with sen = 0 (reception, 7-bit address) ................................................... 158 i 2 c slave mode with sen = 1 (reception, 10-bit address) ................................................. 165 i 2 c slave mode with sen = 1 (reception, 7-bit address) ................................................... 164 low-voltage detect .................................................. 262 master ssp i 2 c bus data ........................................ 355 master ssp i 2 c bus start/stop bits ......................... 355 parallel slave port (pic18f248 and pic18f458) ............................................... 348 parallel slave port read .......................................... 108 parallel slave port write........................................... 107 pwm direction change ............................................ 139 pwm direction change at near 100% duty cycle .............................................. 139 pwm output ............................................................. 128 repeated start condition ......................................... 172 reset, watchdog timer (wdt), oscillator start-up timer (ost), power-up timer (pwrt) .................................. 345 slave mode general call address sequence (7 or 10-bit address mode)............................... 166 slave synchronization .............................................. 149 slow rise time (mclr tied to v dd ) ......................... 29 spi master mode...................................................... 148 spi master mode example (cke = 0) ...................... 349 spi master mode example (cke = 1) ...................... 350 spi slave mode (with cke = 0)................................ 150 spi slave mode (with cke = 1)................................ 150 spi slave mode example (cke = 0) ........................ 351 spi slave mode example (cke = 1) ........................ 352 stop condition receive or transmit mode.................................................. 176 time-out sequence on por w/pll enabled (mclr tied to v dd ) ........................................... 29 time-out sequence on power-up (mclr not tied to v dd ) case 1 ................................................................ 28 case 2 ................................................................ 28 time-out sequence on power-up (mclr tied to v dd ) ........................................... 28 timer0 and timer1 external clock ........................... 346 transition between timer1 and osc1 (hs with pll)........................................... 22 transition between timer1 and osc1 (hs, xt, lp) ............................................ 21 transition between timer1 and osc1 (rc, ec) .................................................. 22 pic18fxx8 ds41159e-page 396 ? 2006 microchip technology inc. transition from osc1 to timer1 oscillator................................................. 21 usart asynchronous reception ............................. 192 usart asynchronous transmission........................ 190 usart asynchronous transmission (back to back)................................................... 190 usart synchronous receive (master/slave)................................................... 357 usart synchronous reception (master mode, sren)....................................... 195 usart synchronous transmission ......................... 194 usart synchronous transmission (master/slave)................................................... 357 usart synchronous transmission (through txen)................................................ 194 wake-up from sleep via interrupt ............................. 275 timing diagrams and specifications................................. 343 a/d conversion requirements ................................. 359 a/d converter characteristics .................................. 358 capture/compare/pwm requirements (ccp1 and eccp1) .......................................... 347 clko and i/o timing requirements.................................................... 344 example spi mode requirements (master mode, cke = 0) ................................... 349 example spi mode requirements (master mode, cke = 1) ................................... 350 example spi mode requirements (slave mode, cke = 0) ..................................... 351 example spi slave mode requirements (cke = 1)................................... 352 external clock timing requirements........................ 343 i 2 c bus data requirements (slave mode)..................................................... 354 i 2 c bus start/stop bits requirements (slave mode)..................................................... 353 master ssp i 2 c bus data requirements.................................................... 356 master ssp i 2 c bus start/stop bits requirements.................................................... 355 parallel slave port requirements (pic18f248 and pic18f458) ........................... 348 pll clock.................................................................. 344 reset, watchdog timer, oscillator start-up timer, power-up timer, brown-out reset and low-voltage detect requirements ........................................ 345 timer0 and timer1 external clock requirements.......................................... 346 usart synchronous receive requirements.................................................... 357 usart synchronous transmission requirements.................................................... 357 tstfsz............................................................................. 321 txsta register brgh bit .................................................................. 185 u usart.............................................................................. 183 asynchronous mode ................................................. 189 reception ......................................................... 191 setting up 9-bit mode with address detect ......................................... 191 transmission .................................................... 189 asynchronous reception.......................................... 192 asynchronous transmission associated registers........................................ 190 baud rate generator (brg) .................................... 185 associated registers........................................ 185 baud rate error, calculating............................ 185 baud rate formula .......................................... 185 baud rates for asynchronous mode (brgh = 0)............................................... 187 baud rates for asynchronous mode (brgh = 1)............................................... 188 baud rates for synchronous mode.................. 186 high baud rate select (brgh bit) .................. 185 sampling........................................................... 185 serial port enable (spen) bit .................................. 183 synchronous master mode....................................... 193 reception ......................................................... 195 transmission .................................................... 193 synchronous master reception associated registers........................................ 195 synchronous master transmission associated registers........................................ 193 synchronous slave mode......................................... 196 reception ......................................................... 196 transmission .................................................... 196 synchronous slave reception.................................. 197 synchronous slave transmission associated registers........................................ 197 v voltage reference specifications..................................... 340 w wake-up from sleep ................................................. 265, 274 using interrupts ........................................................ 274 watchdog timer (wdt)............................................ 265, 272 associated registers ................................................ 273 control register........................................................ 272 postscaler................................................................. 273 programming considerations ................................... 272 rc oscillator............................................................. 272 time-out period ........................................................ 272 wcol ....................................................... 171, 172, 173, 176 wcol status flag.................................... 171, 172, 173, 176 wdt. see watchdog timer. www, on-line support .................... ................................... 5 x xorlw............................................................................. 321 xorwf ............................................................................ 322 ? 2006 microchip technology inc. advance information ds41159e-page 397 pic18fxx8 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com pic18fxx8 ds41159e-page 398 advance information ? 2006 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41159e pic18fxx8 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? ? 2006 microchip technology inc. ds41159e-page 399 pic18fxx8 pic18fxx8 product identification system to order or obtain information, e.g. , on pricing or delivery, refer to the factory or the listed sales office. part no. x /xx xxx pattern package temperature range device device pic18f248/258 (1) , pic18f448/458 (1) , pic18f248/258t (2) , pic18f448/458t (2) ; v dd range 4.2v to 5.5v pic18lf248/258 (1) , pic18lf448/458 (1) , pic18lf248/258t (2) , pic18lf448/458t (2); v dd range 2.0v to 5.5v temperature range i = -40 c to +85 c(industrial) e= -40 c to +125 c (extended) package pt = tqfp (thin quad flatpack) l=plcc so = soic sp = skinny plastic dip p=pdip pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic18lf258-i/l 301 = industrial temp., plcc package, extended v dd limits, qtp pattern #301. b) pic18lf458-i/pt = industrial temp., tqfp package, extended v dd limits. c) pic18f258-e/l = extended temp., plcc package, normal v dd limits. note 1: f = standard voltage range lf = wide voltage range 2: t = in tape and reel plcc and tqfp packages only. ds41159e-page 400 ? 2006 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta alpharetta, ga tel: 770-640-0034 fax: 770-640-0307 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway habour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7250 fax: 86-29-8833-7256 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - gumi tel: 82-54-473-4301 fax: 82-54-473-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - penang tel: 60-4-646-8870 fax: 60-4-646-5086 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-3910 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 08/29/06 |
Price & Availability of PIC18LF248-ISP
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |